Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
slow clock RC oscillator clock period. If, during the high level period of the slow clock RC oscilla-
tor, less than 8 fast crystal oscillator clock periods have been counted, then a failure is declared.
If a failure of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is detected,
the CFDEV flag is set in the PMC Status Register (PMC_SR), and generates an interrupt if it is
not masked. The interrupt remains active until a read operation in the PMC_SR register. The
user can know the status of the clock failure detector at any time by reading the CFDS bit in the
PMC_SR register.
If the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is selected as the source
clock of MAINCK (MOSCSEL = 1), and if the Master Clock Source is PLLACK or PLLBCK (CSS
= 2 or 3), a clock failure detection automatically forces MAINCK to be the source clock for the
master clock (MCK).Then, regardless of the PMC configuration, a clock failure detection auto-
matically forces the 4/8/12 MHz Fast RC oscillator to be the source clock for MAINCK. If the Fast
RC oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by
the clock failure detection mechanism.
It takes 2 slow clock RC oscillator cycles to detect and switch from the 3 to 20 MHz Crystal, or
Ceramic Resonator-based oscillator, to the 4/8/12 MHz Fast RC Oscillator if the Master Clock
source is Main Clock, or 3 slow clock RC oscillator cycles if the Master Clock source is PLLACK
or PLLBCK.
A clock failure detection activates a fault output that is connected to the Pulse Width Modulator
(PWM) Controller. With this connection, the PWM controller is able to force its outputs and to
protect the driven device, if a clock failure is detected. This fault output remains active until the
defect is detected and until it is cleared by the bit FOCLR in the PMC Fault Output Clear Regis-
ter (PMC_FOCR).
The user can know the status of the fault output at any time by reading the FOS bit in the
PMC_SR register.
27.2.13 Programming Sequence
1. Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Regis-
ter (CKGR_MOR). The user can define a start-up time. This can be achieved by writing a
value in the MOSCXTST field in CKGR_MOR. Once this register has been correctly config-
ured, the user must wait for MOSCXTS field in the PMC_SR register to be set. This can be
done either by polling the status register, or by waiting the interrupt line to be raised if the
associated interrupt to MOSCXTS has been enabled in the PMC_IER register.
Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
The main oscillator will be enabled (MOSCXTS bit set) after 56 Slow Clock Cycles.
2. Checking the Main Oscillator Frequency (Optional):
In some situations the user may need an accurate measure of the main clock frequency. This
measure can be accomplished via the Main Clock Frequency Register (CKGR_MCFR).
Once the MAINFRDY field is set in CKGR_MCFR, the user may read the MAINF field in
CKGR_MCFR. This provides the number of main clock cycles within sixteen slow clock
cycles.
3. Setting PLL and Divider:
All parameters needed to configure PLLA and the divider are located in CKGR_PLLAxR.