Conventions and Notations
© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
1-5
DPM
Defects per Million
EPROM
Erasable Programmable Read Only Memory
FCBGA
Flip Chip Ball Grid Array
FIFO
First In, First Out
VSS
Ground
GPIO
General Purpose Input/Output
HT
HyperTransport™ interface
IDDQ
Direct Drain Quiescent Current
IOMMU
Input/Output Memory Management Unit
JTAG
Joint Test Access Group. An IEEE standard.
MB
Mega Byte
NB
Northbridge
PCI
Peripheral Component Interface
PCIe
®
PCI Express
®
PLL
Phase Locked Loop
POST
Power On Self Test
PD
Pull-down Resistor
PU
Pull-up Resistor
RAS
Reliability, Availability and Serviceability
SB
Southbridge
TBA
To Be Added
VRM
Voltage Regulation Module
Table 1-3 Acronyms and Abbreviations (Continued)
Acronym
Full Expression