© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
Table of Contents-1
Table of Contents
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6
1.2.7
1.2.8
1.2.9
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
Chapter 2: Functional Descriptions
2.1.1
2.1.2
HyperTransport™ Flow Control Buffers
2.3 Multiple Northbridge Support
2.4.1
2.4.2
2.4.3
2.4.4
MSI Interrupt Handling and MSI to HT Interrupt Conversion
............................................................................2-5
2.4.5
Internally Generated Interrupts
2.4.6
2.4.7
Interrupt Routing Architecture
2.5.1
2.5.2
SERR_FATAL# and NON_FATAL_CORR# Pins
.............................................................................................2-7
2.5.3
2.5.4
Suggested Platform Level RAS Sideband Signal Connections
............................................................................2-8
2.5.5
2.5.6
Interrupt Generation on Errors
2.5.7
2.5.8