47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
3-6
Proprietary
Clock Interface
3.4.3
Miscellaneous PCI Express
®
Signals
3.5
Clock Interface
3.6
Power Management Pins
Table 3-4 Miscellaneous PCI Express
®
Signals
Pin Name
Type
Power
Domain
Ground
Domain
Functional Description
PCE_BCALRN
I
VDDA18PCIE
VSSA_PCIE
N Channel Driver Compensation Calibration for Rx and Tx Channels
on Bottom Side.
PCE_BCALRP
I
VDDA18PCIE
VSSA_PCIE
P Channel Driver Compensation Calibration for Rx and Tx Channels
on Bottom Side
PCE_TCALRN
I
VDDA18PCIE
VSSA_PCIE
N Channel Driver Compensation Calibration for Rx and Tx Channels
on Top Side.
PCE_TCALRP
I
VDDA18PCIE
VSSA_PCIE
P Channel Driver Compensation Calibration for Rx and Tx Channels
on Top Side
PCE_RCALRN
I
VDDA18PCIE
VSSA_PCIE
N Channel Driver Compensation Calibration for Rx and Tx Channels
on Right Side.
PCE_RCALRP
I
VDDA18PCIE
VSSA_PCIE
P Channel Driver Compensation Calibration for Rx and Tx Channels
on Right Side
PCIE_RESET_GP
IO[5:1]
I/O
VDDA18PCIE
VSS
PCIe Resets. Except for PCIE_RESET_GPIO3, they can also be
used as GPIOs. There are internal pull-downs of 1.7 k
on these
pins.
Table 3-5 Clock Interface
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
Termination Functional Description
HT_REFCLKP,
HT_REFCLKN
I
VDDA18HTPLL
VSSA_HT
Disabled
HyperTransport™ 100 MHz Clock Differential Pair from
external clock source
GPP1_REFCLKP,
GPP1_REFCLKN
I
VDDA18PCIE
VSSA_PCIE
–
General Purpose 1 Clock Differential Pair. The pair is
connected to an external clock generator on the
motherboard when the General Purpose 1 link is used,
and can be left unconnected if the link is not used.
GPP3_REFCLKP,
GPP3_REFCLKN
I
VDDA18PCIE
VSSA_PCIE
–
General Purpose 3 Clock Differential Pair.
The pair has to
be connected to an external clock generator on the
motherboard whether the General Purpose 3 link is
used or not.
OSCIN
I
VDD18
VSS
Disabled
14.318MHz Reference clock input from the external clock
chip (1.8 volt signaling)
Table 3-6 Power Management Pins
Pin Name
Type
Power
Domain
Ground
Domain Functional Description
ALLOW_LDTSTOP
OD
VDD18
VSS
Allow LDTSTOP. This signal is used by the SR5650 to communicate with the
Southbridge and tell it when it can assert the LDTSTOP# signal.
1 = LDTSTOP# can be asserted
0 = LDTSTOP# has to be de-asserted
LDTSTOP#
I
VDD18
VSS
HyperTransport™ Stop. This signal is generated by the Southbridge and is used to
determine when the HyperTransport link should be disconnected and go into a
low-power state. It is a single-ended signal.
POWERGOOD I
VDD18
VSS
Input from the motherboard signifying that the power to the SR5650 is up and
ready. Signal High means all power planes are valid. It is not observed internally
until it has been high for more than 6 consecutive REFCLK cycles. The rising edge
of this signal is deglitched.
SYSRESET#
I
VDD18
VSS
Global Hardware Reset. This signal comes from the Southbridge.