47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
2-8
Proprietary
RAS Features
syncflood, as well as internal parity errors or fatal errors for which signalling by SERR_FATAL# is enabled. Fatal errors
are identified via the fatal error status bits.
Non-fatal or correctable errors may be likewise signalled via DBG_GPIO3/NON_FATAL_CORR#.
The SERR_FATAL# and NON_FATAL_CORR# pin functionalities are disabled on warm reset.
2.5.3 NMI# and SYNCFLOODIN#
The SR5650 may configure the DFT_GPIO0/NMI# pin as an input pin for triggering an upstream NMI packet to the
processor complex. The pin should be driven by a BMC. An internal sticky status bit records the use of the NMI# pin.
Also, the SR5650 may configure the DFT_GPIO5/SYNCFLOODIN# pin as an input pin for triggering a HyperTransport
syncflood event. The pin should driven by a BMC. An internal sticky status bit records the use of the SYNCFLOODIN#
pin.
2.5.4 Suggested Platform Level RAS Sideband Signal Connections
is a logical diagram showing suggestions for RAS sideband signal connections at the platform level .