47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
Table of Contents-2
Proprietary
2.5.9
HT Syncflood Based on PCIe® Error
Express®
.................................................................................................................................................................. 2-12
2.6.1
2.6.2
Chapter 3: Pin Descriptions and Strap Options
3.2 SR5650 Interface Block Diagram
3.3 CPU HyperTransport™ Interface
3.4.1
PCI Express® Interface for General Purpose External Devices
......................................................................... 3-5
3.4.2
A-Link Express II Interface to Southbridge
3.4.3
Miscellaneous PCI Express® Signals
Chapter 4: Timing Specifications
4.1 HyperTransport™ Bus Timing
4.2 PCI Express® Differential Clock AC Specifications
4.3 HyperTransport™ Reference Clock Timing Parameters
................................................................................................... 4-1
4.4 OSCIN Reference Clock Timing Parameters
4.5.1
4.5.2
Chapter 5: Electrical Characteristics and Physical Data
5.1 Electrical Characteristics
5.1.1
5.1.2
5.2 SR5650 Thermal Characteristics
5.2.1
5.2.2
5.3.1
5.3.2
Board Solder Reflow Process Recommendations
............................................................................................... 5-6
Chapter 6: Power Management and ACPI