47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
2-4
Proprietary
IOMMU
2.2
IOMMU
The SR5650’s IOMMU (Input/Output Memory Management Unit) block provides address translation and protection
services as described in version 1.26 of the
AMD I/O Virtualization Technology (IOMMU) Specification
. The SR5650
also supports the
PCI Express Address Translation Services 1.0 Specification
, which allows the supporting of endpoint
devices to request and cache address translations.
When DMA requests containing virtual addresses are received, the IOMMU looks up the page translation tables located
in the system memory in order to convert the virtual addresses into physical addresses and to verify access privileges.
On-chip caching is provided in order to speed up translation and reduce or eliminate the number of system memory
accesses required. Every PCIe core contains a local translation cache, and the SR5650 also contains a shared global
translation cache.
The SR5650 supports up to 2
16
domains, each of which can utilize a separate 64-bit virtual address space. It supports a
52-bit physical address space.
2.3
Multiple Northbridge Support
Multiple SR5690/5670/5650 (referred to as “SR56x0”below) Northbridges may be implemented in the same system given
enough free HyperTransport links from the processor complex. However, only a single Southbridge may be used. The
SR56x0 attached to the Southbridge is called the primary SR56x0, and any other instance of SR56x0 is called a secondary
SR56x0. The A-Link Express interface on any secondary SR56x0 must be left unconnected, and it cannot be used to
support any PCI Express endpoint devices.
The PWM_GPIO5 pin-strap is used to indicate whether an SR56x0 is a primary or a secondary Northbridge. If no
pull-down resistor is attached on the pin, the internal pull-up resistor on it will set the strap value to “1,” indicating the
device to be a primary Northbridge. On any secondary SR56x0, the PWM_GPIO5 pin-strap must be pulled low.
In the multi-NB mode, special PCI Express messages for functions such as PME may be passed from a secondary SR56x0
to the primary SR56x0 or the Southbridge over the HyperTransport bus. If the SR56x0’s internal IOAPIC is not used,
INTx messages may also be forwarded over the HyperTransport bus to the Southbridge IOAPIC. Peer-to-peer writes
between PCI Express endpoints are also allowed between any SR56x0 and another by routing peer-to-peer requests over
the HyperTransport bus.
Note:
As it is possible to mix-and-match SR5650, SR5670, and SR5690 on the same system, whenever a
multiple-SR5650 configuration is being referred to in this document, it actually represents any combination of SR5650,
SR5670, and SR5690 possible under that situation. Some constrains may apply.
2.4
Interrupt Handling
2.4.1 Legacy INTx Handling
In legacy interrupt mode, all INTx messages must be routed to the Southbridge IOAPIC. The primary NB directs all INTx
messages directly down to the Southbridge IOAPIC. Secondary NBs direct INTx messages up to the processor complex,
where they are broadcast down to all HT devices. See
Section 2.3, “Multiple Northbridge Support‚’ on page 2-4
details.
The 4 legacy interrupts sent by endpoint devices (INT A/B/C/D) may undergo a 2-stage programmable swizzling process
that maps them onto the 8 possible internal INTx messages (INT A/B/C/D/E/F/G/H). The first swizzling stage is
performed by rotating the interrupt message number based upon the bridge device number. The second stage is register
controllable on a per-bridge basis and maps the rotated INT A/B/C/D onto INT E/F/G/H. INT A to H messages sent to the
Southbridge are mapped onto the SB IOAPIC interrupt redirection table entries 16 to 23.
2.4.2 Non-SB IOAPIC Support
The SR5650 supports routing legacy IOAPIC memory-mapped I/O addresses (0xFECx_xxxx) to any PCI Express port to
support endpoint devices with integrated IOAPIC.