PCI Express® Interfaces
© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
3-5
3.4
PCI Express
®
Interfaces
3.4.1
PCI Express
®
Interface for General Purpose External Devices
3.4.2
A-Link Express II Interface to Southbridge
HT_TXCLK[1:0]P,
HT_TXCLK[1:0]N
O
VDDHT
VSS
Transmitter Clock Signal Differential Pair. Forwarded clock signal. Each byte
of TXCAD uses a separate clock signal. Data is transferred on each clock
edge.
HT_TXCTL[1:0]P,
HT_TXCTL[1:0]N
O
VDDHT
VSS
Transmitter Control Differential Pair. The pair is for distinguishing control
packets from data packets. Each byte of TXCAD uses a separate control
signal.
HT_RXCALN
Other
VDDHT
VSS
Receiver Calibration Resistor to HT_RXCALP
HT_RXCALP
Other
VDDHT
VSS
Receiver Calibration Resistor to HT_RXCALN
HT_TXCALP
Other
VDDHT
VSS
Transmitter Calibration Resistor to HTTX_CALN
HT_TXCALN
Other
VDDHT
VSS
Transmitter Calibration Resistor to HTTX_CALP
Table 3-2 PCI Express
®
Interface for General Purpose External Devices
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
Termination Functional Description
GPP1_TX[15:0]P,
GPP1_TX[15:0]N
O
VDDA18PCIE
VSSA_PCIE
50
between
complements
General Purpose 1 Transmit Data Differential Pairs.
Connect to connector[s] for general purpose external
device[s] on the motherboard.
GPP1_RX[15:0]P,
GPP1_RX[15:0]N
I
VDDA18PCIE
VSSA_PCIE
50
between
complements
General Purpose 1 Receive Data Differential Pairs.
Connect to connector[s] for general purpose external
device[s] on the motherboard.
GPP3_TX[5:0]P,
GPP3_TX[5:0]N
O
VDDA18PCIE
VSSA_PCIE
50
between
complements
General Purpose 3 Transmit Data Differential Pairs.
Connect to connector[s] for general purpose external
device[s] on the motherboard.
GPP3_RX[5:0]P,
GPP3_RX[5:0]N
I
VDDA18PCIE
VSSA_PCIE
50
between
complements
General Purpose 3 Receive Data Differential Pairs.
Connect to connector[s] for general purpose external
device[s] on the motherboard.
Table 3-3 1 x 4 Lane A-Link Express II Interface for Southbridge
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
Termination Functional Description
SB_TX[3:0]P,
SB_TX[3:0]N
O
VDDA18PCIE
VSSA_PCIE
50
between
complements
Southbridge Transmit Data Differential Pairs. Connect to the
corresponding Receive Data Differential Pairs on the
Southbridge.
SB_RX[3:0]P,
SB_RX[3:0]N
I
VDDA18PCIE
VSSA_PCIE
50
between
complements
Southbridge Receive Data Differential Pairs. Connect to the
corresponding Transmit Data Differential Pairs on the
Southbridge.
Table 3-1 HyperTransport™ Interface (Continued)
Pin Name
Type
Power
Domain
Ground
Domain
Functional Description