© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
2-1
Chapter 2
Functional Descriptions
This chapter describes the functional operation of the major interfaces of the SR5650 system logic chip.
illustrates the SR5650 internal blocks and interfaces.
Figure 2-1 SR5650 Internal Blocks and Interfaces
2.1
HyperTransport™ Interface
2.1.1 Overview
The SR5650 is optimized to interface with “Shanghai” and subsequent series of AMD server/workstation and desktop
processors through sockets F, AM3, G34, and C32. The SR5650 supports HyperTransport
™
3 (HT3), as well as
HyperTransport 1 (HT1) for backward compatibility and for initial boot-up. For a detailed description of the interface,
please refer to the
HyperTransport I/O Link Specification
from the HyperTransport Consortium.
“HyperTransport™ Interface Block Diagram,”
illustrates the basic blocks of the host bus interface of the SR5650.
HyperTransport™ 3
Unit
CP
U
Int
erf
ac
e
Root
CPU
Southbridge
Complex
A-
Link-E
In
te
rfa
ce
GPP3 Inter
face
PCI
e
(6 La
ne
s f
or 6 po
rts)
Expansion
Slots
(1 x
4 Lanes)
IO Con
tro
ll
er
GP
P1 In
ter
fa
ce
PCI
e
®
Register Interface
(1 x
16 or
2 x 8
Lane
s)
IOMMU
Expansion
Slots