47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
2-12
Proprietary
PCI
Express®
2.5.9 HT Syncflood Based on PCIe
®
Error
The SR5650 has the ability to put the HyperTransport link into the syncflood state when a fatal or non-fatal error is
received on the PCIe interface. This is done in order to help stop data movement within the system.
2.6
PCI
Express
®
2.6.1 PCIe
®
Ports
In total, there are 9 PCIe
®
ports on the SR5650, divided into 3 groups and implemented in hardware as 3 separate cores:
•
PCIE-GPP1: 2 general purpose ports, 16 lanes in total. Width of each port is x8. In the default configuration, the 2
ports are combined to provide a 1 x16 port.
•
PCIE-GPP3: 6 general purpose ports, with 6 lanes in total. They support 6 different configurations with respect to
link widths: 4:2, 4:1:1, 2:2:2, 2:2:1:1, 2:1:1:1:1, and 1:1:1:1:1:1 (default configuration). For details on the possible
configurations for the GPP3 lanes, see
below and .
•
PCIE-SB: The Southbridge port provides a dedicated x4 link to the Southbridge (also referred to as the “A-Link
Express II interface”).
Each port supports the following PCIe functions:
•
PCIe Gen 1 link speeds
•
ASPM L0s and L1 states
•
ACPI power management
•
Endpoint and root complex initiated dynamic link degradation
•
Lane reversal
•
Alternative Routing-ID Interpretation (ARI)
•
Access Control Services (ACS)
•
Advanced Error Reporting (AER)
•
Address Translation Services (ATS)
2.6.2 PCIe
®
Reset Signals
Reset signals to PCIe slots, as well as embedded PCIe devices, must be controlled through one or more
software-controllable GPIO pins instead of the global system reset. It is recommended that unique GPIO pins be used for
each slot or device. The SR5650 has four GPIO pins that may be used for the purpose of driving reset signals
(PCIE_GPIO_RESET[5:4] and PCIE_GPIO_RESET[2:1]). Additional reset GPIO pins may be driven by
platform-specific means such as a super I/O or an I/O expander.
2.7
External Clock Chip
On the SR5650 platform, an external clock chip provides the CPU, PCI Express, and A-Link Express II reference clocks.
For requirements on the clock chip, please refer to the
800-Series IGP Express AMD Platform External Clock Generator
Requirements Specification for Server Platforms
.
Table 2-4 Possible Configurations for the PCI Express
®
General Purpose Links
PCIe Core
Physical Lane
Config. B
Config. C Config. C2 Config. E
Config. K
Config. L
GPP3
GPP3 lane 0
x4
x4
x2
x2
x2
x1
GPP3 lane 1
x1
GPP3 lane 2
x2
x1
x2
x1
GPP3 lane 3
x1
x1
GPP3 lane 4
x2
x1
x2
x1
x1
x1
GPP3 lane 5
x1
x1
x1
x1