© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
4-1
Chapter 4
Timing Specifications
4.1
HyperTransport™ Bus Timing
For HyperTransport™ bus timing information, please refer to specifications by AMD.
4.2
PCI Express
®
Differential Clock AC Specifications
4.3
HyperTransport™ Reference Clock Timing Parameters
Table 4-1 Timing Requirements for PCIe
®
Differential Clocks (GPP1_REFCLK and GPP3_REFCLK at 100MHz)
Symbol
Description
Minimum
Maximum
Unit
Rising Edge Rate
Rising Edge Rate
0.6
4.0
V/ns
Falling Edge Rate
Falling Edge Rate
0.6
4.0
V/ns
T
PERIOD AVG
Average Clock Period Accuracy
-100
+100
ppm
T
PERIOD ABS
Absolute Period (including jitter and spread spectrum
modulation)
9.847
10.203
ns
T
CCJITTER
Cycle to Cycle Jitter
-
150
ps
Duty Cycle
Duty Cycle
40
60
%
Rise-Fall Matching
Rising edge rate () to falling edge rate
(REFCLK-) matching
-
20
%
Table 4-2 Timing Requirements for HyperTransport™ Reference Clock (100MHz)
Symbol
Parameter
Minimum
Maximum
Unit
Note
V
CROSS
Change in Crossing point voltage over all edges
-
140
mV
1
F
Frequency
99.5
100
MHz
2
ppm
Long Term Accuracy
-100
+100
Ppm
3
S
FALL
Output falling edge slew rate
-10
-0.5
V/ns
4, 5
S
RISE
Output rising edge slew rate
0.5
10
V/ns
4,5
T
jc max
Jitter, cycle to cycle
-
150
ps
6
T
j-accumulated
Accumulated jitter over a 10
s period
-1
1
ns
7
V
D(PK-PK)
Peak to Peak Differential Voltage
400
2400
mV
8
V
D
Differential Voltage
200
1200
mV
9
V
D
Change in V
DDC
cycle to cycle
-75
75
mV
10