47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
3-4
Proprietary
SR5650 Interface Block Diagram
3.2
SR5650 Interface Block Diagram
shows the different interfaces on the SR5650. Interface names in
blue
are hyperlinks to the corresponding
sections in this chapter.
Figure 3-1 SR5650 Interface Block Diagram
3.3
CPU HyperTransport™ Interface
Table 3-1 HyperTransport™ Interface
Pin Name
Type
Power
Domain
Ground
Domain
Functional Description
HT_RXCAD[15:0]P,
HT_RXCAD[15:0]N
I
VDDHT
VSS
Receiver Command, Address, and Data Differential Pairs
HT_RXCLK[1:0]P,
HT_RXCLK[1:0]N
I
VDDHT
VSS
Receiver Clock Signal Differential Pair. Forwarded clock signal. Each byte of
RXCAD uses a separate clock signal. Data is transferred on each clock edge.
HT_RXCTL[1:0]P,
HT_RXCTL[1:0]N
I
VDDHT
VSS
Receiver Control Differential Pair. The pair is for distinguishing control packets
from data packets. Each byte of RXCAD uses a separate control signal.
HT_TXCAD[15:0]P,
HT_TXCAD[15:0]N
O
VDDHT
VSS
Transmitter Command, Address, and Data Differential Pairs
HT_RXCAD[15:0]P, HT_RXCAD[15:0]N
HT_RXCLK[1:0]P, HT_RXCLK[1:0]N
HT_RXCTL[1:0]P, HT_RXCTL[1:0]N
HT_TXCTL[1:0]P, HT_TXCTL[1:0]N
HT_RXCALP, HT_RXCALN
HT_TXCALP, HT_TXCALN
HT_TXCLK[1:0]P, HT_TXCLK[1:0]N
HT_TXCAD[15:0]P, HT_TXCAD[15:0]N
SB_TX[3:0]P, SB_TX[3:0]N
SB_RX[3:0]P, SB_RX[3:0]N
OSCIN
SYSRESET#
POWERGOOD
VDDPCIE
VDD18
VDDC
HyperTransport™
Interface
VDDHT
VDDA18HTPLL
PCIe
®
Interface
GPP3_TX[5:0]P, GPP3_TX[5:0]N
GPP3_RX[5:0]P, GPP3_RX[5:0]N
PCE_BCALRP, PCE_BCALRN
HT_REFCLKP, HT_REFCLKN
LDTSTOP#
ALLOW_LDTSTOP
VSS
GPP1_TX[15:0]P, GPP1_TX[15:0]N
GPP1_RX[15:0]P, GPP1_RX[15:0]N
PCIE_RESET_GPIO[5:1]
VDDA18PCIE
GPP3_REFCLKP, GPP3_REFCLKN
GPP1_REFCLKP, GPP1_REFCLKN
PCE_RCALRP, PCE_RCALRN
PCE_TCALRP, PCE_TCALRN
VDDHTTX
TESTMODE
I2C_CLK
I2C_DATA
STRP_DATA
DFT_GPIO5/SYNCFLOODIN#
DBG_GPIO0/SERR_FATAL#
THERMALDIODE_P
THERMALDIODE_N
DFT_GPIO[4:1]
DFT_GPIO0/NMI#
DBG_GPIO[2:1]
DBG_GPIO3/NON_FATAL_CORR#
PWM_GPIO[6:1]