47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
2-6
Proprietary
Interrupt Handling
Figure 2-4 Interrupt Routing Paths in Legacy Mode
2.4.7.2 Legacy Mode with Integrated IOAPIC
For both the primary and secondary SR5650s
,
legacy INTx messages are routed to the integrated IOAPICs of the
SR5650s, which generates interrupt requests. These requests are remapped by the IOMMU before being delivered up to
the processor complex. If an INTx message gets directed to an IOAPIC table entry that is not enabled, the IOAPIC sends
the INTx message back to the IOC to go to the SB PIC/IOAPIC.
The routing paths are illustrated in
below.
Figure 2-5 Interrupt Routing Paths in Legacy Mode with Integrated IOAPIC
CPU
SR5650
CPU
SR5650
SB
PCI-E
Endpoint
Device
PCI-E
Endpoint
Device
INTx Message from device attached to primary SR5650
INTx Message from device attached to secondary SR5650
Interrupts from SB IOAPIC
CPU
SB
PCI-E
Endpoint
Device
IOMMU
HT
PCI-
Express
IOAPIC
SR5650
INTx Message from PCI-Express device attached to SR5650
Internal interrupt
Remapped HT Interrupt
SR5650
PCI-E
Endpoint
Device
CPU