47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
2-2
Proprietary
HyperTransport™ Interface
Figure 2-2 HyperTransport™ Interface Block Diagram
The SR5650 HyperTransport bus interface consists of 16 unidirectional differential Command/Address/Data pins, and 2
differential Control pins and 2 differential Clock pins in both the upstream and downstream directions. On power up, the
link is 8-bit wide and runs at a default speed of 400MT/s in HyperTransport 1 mode. After negotiation, carried out by the
HW and SW together, the link width can be brought up to the full 16-bit width and the interface can run up to 5.2GT/s in
HyperTransport 3 mode. In HyperTransport 1 mode, the interface operates by clock-forwarding while in HyperTransport
3 mode, the interface operates by dynamic phase recovery, with frequency information propagated over the clock pins.
The interface is illustrated below in
Figure 2-3, “SR5650 HyperTransport™ Interface Signals.”
The signal name and
direction for each signal is shown with respect to the SR5650. Detailed descriptions of the signals are given in
“CPU HyperTransport™ Interface‚’ on page 3-4
.
I/O Controller
Upstream Arbitration
IOMMU L2
10.4 GB/s to
CPU
Response
Interface
Host Interface
Host
requests
Host read
responses
Host read
responses
DMA requests
DMA
read
response
data
IOMMU
requests
10.4 GB/s from
CPU
Rx PHY
Tx PHY
Rx PHY Interface
Tx PHY Interface
Protocol Receiver
Protocol Transmitter
PCIe
®
Cores