47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
3-10
Proprietary
Strapping Options
3.10
Strapping Options
The SR5650 provides strapping options to define specific operating parameters. The strap values are latched into internal
registers after the assertion of the POWERGOOD signal to the SR5650.
Table 3-10, “Strap Definitions for the SR5650,”
shows the definitions of all the strap functions. These straps are set by one of the following four methods:
•
Allowing the internal pull-up resistors to set all strap values “1”’s automatically.
•
Attaching pull-down resistors to specific strap pins listed in
to set their values to “0”’s.
•
Downloading the strap values from an I
2
C serial EEPROM (for debug purpose only; contact your AMD FAE
representative for details).
•
Setting through an external debug port, if implemented (contact your AMD FAE representative for details).
Table 3-10 Strap Definitions for the SR5650
Strap Function
Strap Pin
Description
PRIMARY_NB
PWM_GPIO5
Indicates whether the device is a primary or a secondary Northbridge on a
multiple-Northbridge platform. See
section 2.3, “Multiple Northbridge Support,”
for details. Do not install a resistor for sinlge-Northbridge platforms.
0: Device is a secondary Northbridge
1: Device is the primary Northbridge (Default)
Reserved
PWM_GPIO[4:2]
Reserved. Make provision for an external pull-down resistor on each of the pins, but do
not install a resistor.
Reserved
DFT_GPIO0/NMI#
Reserved. Make provision for an external pull-down resistor on this pin, but do not install
a resistor.
LOAD_ROM_STRAPS#
DFT_GPIO1
Selects loading of strap values from EEPROM
0: I
2
C master can load strap values from EEPROM if connected, or use hardware
default values if not connected
1: Use hardware default values (Default)
STRAP_PCIE_GPP_CFG
DFT_GPIO[4:2]
General Purpose Link 3 Configuration.
See
below for details.
Reserved
DFT_GPIO5/
SYNCFLOODIN#
Reserved. Make provision for an external pull-down resistor on this pin, but do not install
a resistor.
Table 3-11 Strap Definition for STRAP_PCIE_GPP_CFG
Strap Pin Value
Link Width
Mode
DFT_GPIO4 DFT_GPIO3 DFT_GPIO2
GPP3
Lane
0
GPP3
Lane
1
GPP3
Lane
2
GPP3
Lane
3
GPP3
Lane
4
GPP3
Lane
5
1
1
1
Hardware default (Mode L) or EEPROM strap
values
(Default)
-
1
1
0
Hardware default (Mode L) or EEPROM strap
values
-
1
0
1
x2
x2
x2
C2
1
0
0
x2
x2
x1
x1
K
0
1
1
x2
x1
x1
x1
x1
E
0
1
0
x1
x1
x1
x1
x1
x1
L (Hardware
Default)
0
0
1
x4
x1
x1
C
0
0
0
x4
x2
B
Note:
If the pin straps instead of strap values from EEPROM are used, the GPP3
configuration will then be determined according to this table and cannot be changed after
the system has been powered up.