IDT Tsi84 User Manual Download

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6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775

Printed in U.S.A.

Tsi384

™

Evaluation Board User Manual

60E1000_MA001_08

September 2009

Summary of Contents for Tsi84

Page 1: ...ek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2009 Integrated Device Technology Inc Tsi384 Evaluation Board User Manual 60E1000_MA001_0...

Page 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Page 3: ...3 1 4 2 Power Requirements 13 1 4 3 Power Sequencing 15 1 4 4 System Power Design 15 1 5 Clock Management 16 1 5 1 PCI X 16 1 5 2 System Clock Distribution 17 1 6 Other Interfaces 18 1 6 1 JTAG Interf...

Page 4: ...ents 4 Tsi384 Evaluation Board User Manual 60E1000_MA001_08 Integrated Device Technology www idt com 2 4 2 J3 ATX Power Connector 33 2 4 3 P1 x4 PCIe Finger Connector 33 2 5 LEDs 34 3 Bill of Material...

Page 5: ...ision 1 0 PCI X Addendum to PCI Local Bus Specification Revision 1 0a Acronyms Revision History 60E1000_MA001_08 Formal September 2009 This document was rebranded as IDT It does not include any techni...

Page 6: ...ersion of the document There are no technical differences between this document and the previous version Evaluation Board Changes Assembly E1000_AS001_03 Item Previous Usage Definition New Usage Defin...

Page 7: ...0E1000_MA001_01 Formal March 2007 This is the first version of the Tsi384 Evaluation Board User Manual This document supports the Revision 1 0 Assembly number E1000_AS001_01 version of the Tsi384 eval...

Page 8: ...About this Document 8 Tsi384 Evaluation Board User Manual 60E1000_MA001_08 Integrated Device Technology www idt com...

Page 9: ...ge 13 Clock Management on page 16 Other Interfaces on page 18 Hardware Reset on page 18 Logic Analyzer Connectivity on page 18 1 1 Overview The key features of the Tsi384 evaluation board include the...

Page 10: ...rs are compliant with the PCI X 2 0b specification Appropriate clearance is provided such that up to three PCI X cards can be inserted for testing while the board is in an open chassis standard ATX ca...

Page 11: ...connector top slot 2K ohms to AD16 Device 0 Slot 1 Vertical middle slot 2K ohms to AD19 Device 3 Slot 2 Vertical lower slot 2K ohms to AD18 Device 2 The 2K ohm resistor value is consistent with the ab...

Page 12: ...m must provide the REFCLK and PERSTN signals The PCIe interface has the following design elements Supports Hot insertion and removal Mid bus logic analyzer pads for PCIe RXD TXD signal probing AC coup...

Page 13: ...nd implementation for the Tsi384 is as follows The target power draw of the Tsi384 is a maximum of 2 Watts all supplies combined The supplies to the Tsi384 are controlled during ramp up using enable p...

Page 14: ...ired to the PCI X without violating the specification while drawing power from only a x4 PCIe system Up to 23W not including regulator efficiency losses can be made available The evaluation board prov...

Page 15: ...are provided with the required power 1 4 3 Power Sequencing On power up the card power sequencing is as follows 1 1 2V powered on 2 PCI X I O slot power and pull ups and Tsi384 3 3V 12V 12V 5V PCI are...

Page 16: ...evaluation board supports master and slave clocking for PCI X Master When in master mode the Tsi384 generates the required PCI X clock for all slots Slave When in slave mode an on board selectable 25...

Page 17: ...CIe clock sources are multiplexed with an analog multiplexer to select between the system clock or on board clock see Figure 3 1 5 2 System Clock Distribution Figure 3 shows the distribution of the sy...

Page 18: ...Tn is muxed with the board s reset controller Warm reset This reset is activated by a push button reset on the board Hot reset This reset is activated by the in band message sent by the root complex N...

Page 19: ...the following Switches on page 19 Shunt Jumpers on page 26 Debug Headers on page 28 Connectors on page 32 LEDs on page 34 2 1 Switches 2 1 1 DIP Switches Switches S1 to S6 combine four small slide sw...

Page 20: ...2 Configurable Options 20 Tsi384 Evaluation Board User Manual 60E1000_MA001_08 Integrated Device Technology www idt com Figure 6 Switch Locations SW1 S8 S7 S3 S4 S1 S2 S5 S6 SW2...

Page 21: ...Forces Tsi384 s M66EN input to ground OFF Tsi384 s M66EN input has a weak pull up to 3 3V 4 PCI_SEL100 setting ON ON Forces Tsi384 s PCI_SEL100 input to ground OFF Tsi384 s PCI_SEL100 input has a wea...

Page 22: ...ee PCIXCAP low ON x ON OFF PCIXCAP Low M666EN Low PCI_SEL100 High PCI 25 MHz ON x ON ON PCIXCAP Low M666EN Low PCI_SEL100 Low PCI 33 MHz Table 10 S2 Settings Switch Number Description Default Setting...

Page 23: ...ternal clock source is used an on board PLL is used to set the proper bus clock frequency Table 11 contains the clock frequency settings for S3 Table 11 S3 Settings Switch Number Description Default S...

Page 24: ...for PLL is reference clock from connector J10 OFF Clock source for PLL is a 25 MHz oscillator 3 PLL select OFF ON PLL is bypassed OFF PLL is enabled External clock source is multiplied as per S3 setti...

Page 25: ...er Description Default Setting On Off Setting 1 Clock Master option OFF ON Tsi384 is clock slave on the PCI X bus OFF Tsi384 is clock master on the PCI X bus clock master mode 2 Internal arbiter optio...

Page 26: ...nual 60E1000_MA001_08 Integrated Device Technology www idt com 2 2 Shunt Jumpers Shunt jumpers are used to control special features on the board see Figure 7 These jumpers are explained in the followi...

Page 27: ...Jumper J6 is used to bypass the On Off push button to enable the ATX power supply 2 2 3 J21 Shunt Jumper J21 is used to force the Tsi384 into a special debug mode This jumper is not installed Table 1...

Page 28: ...ion Board User Manual 60E1000_MA001_08 Integrated Device Technology www idt com 2 3 Debug Headers Debug headers are used to connect to signals on the board This section provides header pinouts Figure...

Page 29: ...ted Device Technology www idt com 2 3 1 J22 Tsi384 JTAG Table 18 J22 Pin Assignment Pin Number Signal Assignment J22 Pin Location 1 TDO 2 NC 3 TDI 4 3 3V 5 NC 6 3 3V 7 TCK 8 NC 9 TMS 10 NC 11 NC 12 GN...

Page 30: ...E_TXD_EDG_P0 2 GND 3 PCIE_TXD_EDG_N0 4 PCIE_RXD_EDG_P0 5 GND 6 PCIE_RXD_EDG_N0 7 PCIE_TXD_EDG_P1 8 GND 9 PCIE_TXD_EDG_N1 10 PCIE_RXD_EDG_P1 11 GND 12 PCIE_RXD_EDG_N1 13 PCIE_TXD_EDG_P2 14 GND 15 PCIE_...

Page 31: ...Board User Manual 60E1000_MA001_08 Integrated Device Technology www idt com 2 3 3 J38 CPLD JTAG Table 20 J38 Pin Assignment Pin Signal Assignment J38 Pin Location 1 TCK 2 GND 3 TDO 4 3 3V 5 TMS 6 NC...

Page 32: ...Technology www idt com 2 4 Connectors Figure 9 Board Connector Location 2 4 1 J2 J36 J37 Connectors J2 J36 and J37 are used to connect a plug in card to the Tsi384 s PCI X Interface The connectors pin...

Page 33: ...a PCIe system 2 4 3 P1 x4 PCIe Finger Connector The pin assignment for the finger connector is as per the PCIe standard Note that the JTAG signals TDI and TDO are connected together on the board Tabl...

Page 34: ...2 Configurable Options 34 Tsi384 Evaluation Board User Manual 60E1000_MA001_08 Integrated Device Technology www idt com 2 5 LEDs Figure 10 LED Location D2 D8 D1 D24 D25 D11 D18 D19 D22...

Page 35: ...bus at 133 MHz D18 PCIX100 PCI X bus at 100 MHz D19 PCIe lane 2 valid Valid PCIe connection on lane 2 D2 12V ON when 12V rail is active D20 PCIe lane 0 valid Valid PCIe connection on lane 0 D21 PCIe...

Page 36: ...2 Configurable Options 36 Tsi384 Evaluation Board User Manual 60E1000_MA001_08 Integrated Device Technology www idt com...

Page 37: ...T2A AVX CAPC0402 X7R CER SMT 0 01UF 10 10V 0402 113 C17 21 C23 25 C38 C48 49 C52 C60 61 C64 71 C105 C108 127 C130 139 C141 142 C144 161 C163 164 C166 171 C176 C179 C184 186 C190 C192 C194 196 C198 C20...

Page 38: ...25 HSMG C150 AGILENT LED_HSMG C150 GREEN LED UNTINTED DIFFUSED 1 F1 R154 010 LITTLEFUSE FUSE_154 SMT FUSE BLOCK FOR FAST 10AFUSE INCLUDED 4 FB1 2 FB4 FB7 BLM18AG601SN1 D MURATA FB_0603 SMT FERRITE BEA...

Page 39: ...7 R146 R152 R157 R187 R198 R207 R226 R241 242 R256 R283 ERJ 3GEYJ822V PANASONIC RESC0603 RES SMT 8 2K OHM 0 1W 5 0603 9 R46 48 R76 R80 R92 R210 R243 R274 ERJ 3GEYJ103V PANASONIC RESC0603 RES SMT 10K O...

Page 40: ...X PANASONIC RESC0402 RES SMT 100 OHM 06W 1 0402 2 R223 R225 9C06031A0R00JL HFT YAGEO RESC0603 RES SMT 0 OHM 0 1W 5 0603 1 R228 ERJ 3GEYJ223V PANASONIC RESC0603 RES SMT 22K OHM 0 1W 5 0603 2 R231 232 E...

Page 41: ...DE PCI EXPRESS TOPCI XBRIDGE 1 U12 ICS557G 08 IDT TSSOP65P64 16 2 1 MULTIPLEXER CHIP FOR PCIEXPRESS 1 U15 TL7702BCD TI SOIC127P6 8 PORGENERATOR 3 5 18VVCC 2 U16 U18 NC7SZ08M5X FAIRCHILD SOT23 5 TINY L...

Page 42: ...3 Bill of Materials 42 Tsi384 Evaluation Board User Manual 60E1000_MA001_08 Integrated Device Technology www idt com...

Page 43: ...r products The information contained herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for any...

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