RAS Features
© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
2-9
Figure 2-7 Suggested Platform Level RAS Sideband Signal Connections
2.5.5 Error Reporting and Logging
2.5.5.1 PCI Error Logging
The SR5650 implements all PCI standard error logging bits for all on-board devices and functions including the host
bridge device, IOMMU, and PCI Express bridges.
2.5.5.2 PCIe
®
Advanced Error Reporting
The SR5650 PCIe
®
cores implement the optional Advanced Error Reporting (AER) feature mechanism in the
PCI
Express 2.0 Base Specification
. Errors are logged for received packet errors such as poisoned data, malformed TLP, and
etc. within the PCIe core and are accessible via the bridge configuration spaces.
SR5650
BMC, SuperIO or other GPIO
source
SP5100
DBG_GPIO0/
SERR_FATAL#
DBG_GPIO3/
NON_FATAL_CORR#
Attach to a pin that can
generate SMI# like
USB_OC5#/IR_TX0/
GPM5#
DFT_GPIO0/NMI#
DFT_GPIO5/
SYNCFLOODIN#
Enable only after
reset. This is a pin-
strap sampled
shortly after
powergood
Enable signals
should default to
logic 0 on reset/
powergood
Add option to drive
SYNCFLOODIN#
pins on all SR5650s
in the system
SERR_FATAL# and
NON_FATAL_CORR#
from other SR5650s.
These are buffered to help
isolate the failing device.
S/W path to
trigger NMI#
pin
Enable only after
reset. This is a pin-
strap sampled
shortly after
powergood
PCIe
®
From NMI button and
MCARD_NMIBTN_L
OPMA pin
To
SYS_NMIBTN_L
OPMA pin
GPIO Expander
attached to OPMA
SMBus (either private
0 or private 1 SMBus
segments).
Alternately, this can
connect directly to a
BMC
SCL/SDA
Interrupt line to
Sys_SMBUS_IO_EXP_INTR_L
OPMA pin
Separate connections to
debug pins and GPIO
expander for each SR5650
in the system
NMI# only needs to
be connected on
the primary SR5650