47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
4-2
Proprietary
OSCIN Reference Clock Timing Parameters
4.4
OSCIN Reference Clock Timing Parameters
4.5
Power Rail Sequence
For the purpose of power rail sequencing, the power rails of the SR5650 are divided into groupings
described in Table 4-4 below.
DC
Duty Cycle
45
55
%
11
Notes:
More details are available in
AMD HyperTransport 3.0 Reference Clock Specification
and
AMD Family 10h Processor Reference Clock
Parameters
, document # 34864
1 Single-ended measurement at crossing point. Value is maximum-minimum over all time. DC Value of common mode is not important
due to blocking cap.
2 Minimum frequency is a consequence of 0.5% down spread spectrum.
3 Measured with spread spectrum turned off.
4 Only simulated at the receive die pad. This parameter is intended to give guidance for simulation. It cannot be tested on a tester but is
guaranteed by design.
5 Differential measurement through the range of ±100mV, differential signal must remain monotonic and within slew rate specification
when crossing through this region.
6 T
jc
max
is the maximum difference of t
CYCLE
between any two adjacent cycles.
7 Accumulated T
jc
over a 10
s time period, measured with JIT2 TIE at 50ps interval.
8 V
D(PK-PK)
is the overall magnitude of the differential signal.
9 V
D(min)
is the amplitude of the ring-back differential measurement, guaranteed by design that the ring-back will not cross 0V V
D
.
V
D(max)
is the largest amplitude allowed.
10 The difference in magnitude of two adjacent V
DDC
measurements. V
DDC
is the stable post overshoot and ring-back part of the signal.
11 Defined as t
HIGH
/t
CYCLE
Table 4-3 Timing Requirements for OSCIN Reference Clock (14.3181818MHz)
Symbol
Parameter
Min
Typical
Max
Unit
Note
TIP
REFCLK Period
0.037
–
1.1
s
1
FIP
REFCLK Frequency
0.9
–
27
MHz
2
TIH
REFCLK High Time
2.0
–
–
ns
TIL
REFCLK Low Time
2.0
–
–
ns
TIR
REFCLK Rise Time
–
–
1.5
ns
TIF
REFCLK Fall Time
–
–
1.5
ns
TIJCC
REFCLK Cycle-to-Cycle Jitter Requirement
–
–
200
ps
TIJPP
REFCLK Peak-to-Peak Jitter Requirement
–
–
200
ps
1
TIJLT
REFCLK Long Term Jitter Requirement (1
s
after scope trigger)
–
–
500
ps
Notes:
1 Time intervals measured at 50% threshold point.
2 FIP is the reciprocal of TIP.
Table 4-4 Power Rail Groupings for the SR5650
Group Name
Power rail name
Voltage
ACPI
STATE
Description
VDDC
VDDC
1.1V
S0-S2
Core power
VDDPCIE
VDDPCIE
1.1V
S0-S2
PCI Express
®
main IO power
VDDHTTX
VDDHTTX
1.2V
S0-S2
HyperTransport™ transmit interface IO
power
HT_1.1V
VDDHT
1.1V
S0-S2
HyperTransport interface digital IO power
Table 4-2 Timing Requirements for HyperTransport™ Reference Clock (100MHz) (Continued)
Symbol
Parameter
Minimum
Maximum
Unit
Note