Xilinx AMS101 User Manual Download

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AMS101 Evaluation
Card

User Guide

UG886 (v1.3) November 6, 2013

Summary of Contents for AMS101

Page 1: ...AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013...

Page 2: ...tomotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL SAFE PERFORMANCE SUCH AS APPLICATIONS RELATED TO I THE DEPLOY...

Page 3: ...In step 1 page 12 download information changed In step 7 page 16 the AC701 kit and kit documentation references were added Various changes were added to step 9 page 18 Added section Power Monitoring w...

Page 4: ...AMS101 Evaluation Card User Guide www xilinx com UG886 v1 3 November 6 2013...

Page 5: ...ator Tool XADC Configuration 38 XADC Performance Tests 41 AMS Demonstration 44 Appendix A Targeted Design Platforms Schematics and Dynamic Performance Metric Calculation Methodology Supported Targeted...

Page 6: ...6 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 Appendix D Regulatory and Compliance Information Declaration of Conformity 55 Directives 55 Standards 55 Markings 56...

Page 7: ...designs are supplied for the ZC702 KC705 AC701 and VC707 base boards Download these files from either the individual kit support pages or the AMS101 Evaluation Card website For convenience the KC705 F...

Page 8: ...Evaluation Card Overview X Ref Target Figure 1 1 Figure 1 1 KC705 Evaluation Board with the AMS101 Evaluation Card Installed UG886_c1_01_091012 XADC Header Under AMS101 Card AMS101 Evaluation Card X R...

Page 9: ...cription 1 Jumpers to select DAC or external signal source 2 20 pin connector to the XADC header on the FPGA or AP SoC base board 3 Pins allow for external analog input signals 4 Digital I O level tra...

Page 10: ...10 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 Chapter 1 AMS101 Evaluation Card Overview...

Page 11: ...rdware and software that comprise the AMS evaluation platform AMS Evaluation Platform Features The AMS evaluation platform provides A complete XADC and AMS evaluation solution An onboard signal source...

Page 12: ...t Page Click the setup exe file to install the National Instruments LabVIEW RunTime Engine needed to host the AMS Evaluator tool The GUI itself has been built using National Instruments LabVIEW 2011 s...

Page 13: ...er the USB UART connection to the PC and the JTAG Standard A plug to Micro B plug USB programming cable Figure 2 3 shows how to connect these on the KC705 base board Caution Do not turn on the power s...

Page 14: ...XADC header socket are keyed to align properly Pin 1 on the XADC header needs to connect to pin 1 of the 20 pin connector on the AMS101 evaluation card Figure 2 4 shows this connection X Ref Target F...

Page 15: ...able 2 1 AMS101 Evaluation Card Jumper Configuration Notes Callout Reference Designator Component Description Notes Schematics 1 J2 Jumper External signal source to VP positive analog input Figure A 2...

Page 16: ...See the individual kit AC701 ZC702 KC705 or VC707 Getting Started Guides or the 7 Series FPGA AMS Targeted Reference Design User Guide UG960 Ref 1 for more specific instructions on downloading the des...

Page 17: ...ecutable file If the AMS Evaluator tool GUI was successfully installed an icon should be displayed on the desktop and in the Windows start menu see Figure 2 8 To open the AMS Evaluator tool GUI click...

Page 18: ...o and Imaging Kit Getting Started Guide UG926 Ref 4 Artix 7 FPGA AC701 Evaluation Kit Getting Started Guide UG967 Ref 5 Set the USB UART connection to a known port in the Device Manager as follows Rig...

Page 19: ...AMS101 Evaluation Card User Guide www xilinx com 19 UG886 v1 3 November 6 2013 Quick Start X Ref Target Figure 2 10 Figure 2 10 UART USB Port in Device Manager UG886_c2_10_092512...

Page 20: ...the GUI as show in Figure 2 11 Then click the Connect button After the AMS Evaluator tool is connected the kit name is displayed below the green Connected circle If the AMS Evaluator tool is unable to...

Page 21: ...orm measurement tests on the XADC Collect Time Domain Data To collect time domain data press the Collect Data button shown in Figure 2 12 A sine wave should display on the screen This sine wave has be...

Page 22: ...iewed in the time domain The signal to noise ratio total harmonic distortion effective number of bits ENOB and other AC parameters are calculated and displayed in the data panel below the FFT plot as...

Page 23: ...d click the Collect Data button After a short wait both the integral and differential non linearity data is displayed on two separate plots along with the minimum and maximum values at the bottom of t...

Page 24: ...rs as shown in Figure 2 15 Power Monitoring with XADC on AC701 The AC701 evaluation board and AMS Evaluator tool offer a complete system monitoring solution The AC701 uses the XADC to measure voltage...

Page 25: ...rocessor program running as part of the AC701 AMS Targeted Reference Design The current sense values of 1 8V supply 3 3V supply MGTAVCC and MGTAVTT along with voltage levels of 3 3V supply MGTAVCC and...

Page 26: ...l is displayed in the Power Monitor tab on the AMS Evaluator GUI as shown in Figure 2 16 The Power Monitor tab is designed specifically for the AC701 board and is not available on the other AMS Target...

Page 27: ...e select one or more of the existing voltage rails and select the desired new rails Figure 2 17 and Figure 2 18 show voltage current and power measurements of the remaining five rails VCCO_ADJ the 1 8...

Page 28: ...AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 Chapter 2 AMS101 Evaluation Card Quick Start X Ref Target Figure 2 18 Figure 2 18 AC701 Power Monitor Design Measuring MGTAVCC and MGTAVTT...

Page 29: ...Converter User Guide UG480 Ref 6 This evaluation can be done using either an external signal source or the DAC that is present on the card Figure 3 1 shows the block diagram of the card X Ref Target...

Page 30: ...q 7000 SoC base boards The XADC header provides a means to connect the analog inputs of the XADC to the AMS101 evaluation card circuitry as well as providing a reference power and DAC control signals...

Page 31: ...voltage to the DAC Power Supplies The circuitry on the AMS101 evaluation card receives 5V power through the FPGA base board across the XADC header Board Setup Because of the level of flexibility of t...

Page 32: ...the positive XADC inputs VP VAUX0P and VAUX8P DAC B always supplies the output to the negative XADC inputs VN VAUX0N and VAUX8N X Ref Target Figure 3 3 Figure 3 3 Use Case 1 Block Diagram DAC A DAC B...

Page 33: ...offset always supplies the analog voltage to the negative XADC inputs VN VAUXN0 and VAUXN8 For simplicity on the AMS101 evaluation card all three positive XADC inputs VP VAUXP0 and VAUXP8 have been sh...

Page 34: ...get Figure 3 6 Figure 3 6 Use Case 2 Jumper Configurations for Single Ended External Analog Source Jumper J3 3 2 1 1 2 Jumper J5 Apply Negative Analog Input Voltage with Vn Offset Window in AMS Evalua...

Page 35: ...at J2 and J6 pins 1 for both J2 and J6 See Figure 3 8 X Ref Target Figure 3 8 Figure 3 8 Use Case 3 Jumper Configurations Differential External Analog Source Jumper J3 Jumper J6 3 2 1 1 2 Jumper J5 A...

Page 36: ...36 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 Chapter 3 AMS101 Evaluation Hardware...

Page 37: ...Monitor the internal supply voltage and temperature sensors Export measurement results to a CSV file Leverage the FPGA to improve the performance of the XADC using Xilinx Analog Mixed Signal AMS tech...

Page 38: ...t can swing between 0 and 1V Bipolar inputs allow both analog inputs to swing 500 mV with a common mode range between 0 and 1V Single channel mode measures data on the VP VN channels Simultaneous samp...

Page 39: ...clock it receives at the block level The clock divider register of the XADC defines the division factor The GUI gives direct access to it see Figure 4 4 A clock divide ratio can be input directly or...

Page 40: ...l of the DAC through the DAC control panel on the GUI as shown in Figure 4 5 The VP and VN offset fields can be used to define the DC level of each output of the DAC VP corresponds to DACB and VN corr...

Page 41: ...mance tests Time Domain The Time Domain tab gives access to XADC data without any post processing In single channel mode when the Collect Data button is clicked 4 096 sequential XADC results are taken...

Page 42: ...a Similar to the time domain data collection 4 096 sequential XADC results for VP VN are taken when in single channel mode and 4 096 XADC results of VAUX0 and 4 096 XADC results of VAUX8 are taken in...

Page 43: ...l digitized by the XADC when the XADC is in default mode or when they are enabled as part of the channel sequence of the XADC When the Sensor Data tab is selected all of the XADC settings are stored i...

Page 44: ...the AMS Evaluator tool without any filtering or decimation The decimation function is carried out in the FPGA using very little resources The core building block is a decimate by 2 block It first pas...

Page 45: ...rd Typical Results with Multiple Base Boards Base Board Effective Number of Bits ENOB Signal to Noise Ratio SNR dB Decimation 1 Decimation 16 Decimation 1 Decimation 16 ZC706 10 6 12 3 65 8 76 6 AC701...

Page 46: ...46 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 Chapter 4 AMS Evaluator Tool...

Page 47: ...upported Targeted Design Platforms Supported targeted design platforms include the AC701 KC705 VC707 and ZC702 targeted design platforms Supported demonstration design platforms include the ZC706 and...

Page 48: ...1 C11 3300PF 25V X7R U3_VREF DACOUTA 3 DACOUTB 3 2 1 R17 DACOUTA_R 2 1 R13 2 1 R6 2 1 R7 2 1 R3 2 3 1 4 8 7 6 5 U2 NC NC NC XADC_VCC5V0 XADC_AGND 1 2 C7 0 1UF 25V X5R XADC_AGND 2 1 R8 1 00K 1 16W 1 2...

Page 49: ...st five harmonics SFDR is a measure of the difference between the magnitude of the largest spur and the magnitude of the fundamental in dB ENOB is calculated directly from the SINAD number X Ref Targe...

Page 50: ...50 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 Appendix A Targeted Design Platforms Schematics and Dynamic Performance Metric Calculation...

Page 51: ...d 2 J42 Not in place See KC705 Evaluation Board for the Kintex 7 FPGA User Guide UG810 Ref 7 Jumper Settings for the VC707 Board To enable AMS evaluation ensure the VC707 board has the following jumpe...

Page 52: ...ND J14 In place XADC VCC5V0 J52 In place between pins 1 and 2 XADC VREP Sel J53 In place between pins 2 and 3 XADC VCC Sel J54 In place between pins 2 and 3 See Zynq 7000 All Programmable SoC ZC706 Ev...

Page 53: ...es AMS101 Evaluation Card AMS101 Evaluation Card documentation AMS101 Evaluation Card Master Answer Record AR 52165 Analog Mixed Signal AMS101 Instructor led Training and Online Training These Xilinx...

Page 54: ...tional Resources 9 ZC702 Evaluation Board for the Zynq 7000 XC7Z020 All Programmable SoC User Guide UG850 10 Zynq 7000 All Programmable SoC ZC706 Evaluation Kit Getting Started Guide ISE Design Suite...

Page 55: ...ectrotechnical Standardization CENELEC IEC standards are maintained by the International Electrotechnical Commission IEC Electromagnetic Compatibility EN 55022 2010 Information Technology Equipment Ra...

Page 56: ...equipment WEEE The affixed product label indicates that the user must not discard this electrical or electronic product in domestic household waste This product complies with Directive 2002 95 EC on t...

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