47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
7-2
Proprietary
XOR Tree
Figure 7-1 XOR Tree
Pin A is assigned to the output direction, and pins B through F are assigned to the input direction. It can be seen that after
all pins B to F are assigned to logic 0 or 1, a logic change in any one of these pins will toggle the output pin A.
The following is the truth table for the XOR tree shown in
The XOR start signal is assumed to be logic 1.
7.3.2
Description of the XOR Tree for the SR5650
The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the
TDO Pin. Refer to
for the list of the signals included on the XOR tree. There is no specific order to these
signals in the tree. A toggle of any of these balls in the XOR tree will cause the output to toggle.
7.3.3
XOR Tree Activation
To activate the XOR tree and run a XOR test, perform the sequence below:
1. Supply a 10MHz clock to I2C_CLK (Test Mode Clock) and a differential clock pair to the HT_REFCLKP/N,
GPP1_REFCLKP/N and GPP3_REFCLKP/N pins.
2. Set POWERGOOD to 0.
3. Set TESTMODE to 1.
4. Set PCIE_RESET_GPIO2 to 0.
5. Wait 5 or more I2C_CLK cycles.
6. Load JTAG instruction register with the instruction 0001 1111.
7. Load JTAG instruction register with the instruction 0010 0000.
8. Load JTAG instruction register with the instruction 0000 1000.
9. Go to Run-Test_Idle state.
10. Set POWERGOOD to 1.
XOR Start Signal
G
F
E
D
C
B
A
Table 7-2 Example of an XOR Tree
Test Vector
number
Input Pin G
Input Pin F
Input Pin E
Input Pin D
Input Pin C
Input Pin B
Output Pin A
1
0
0
0
0
0
0
1
2
1
0
0
0
0
0
0
3
1
1
0
0
0
0
1
4
1
1
1
0
0
0
0
5
1
1
1
1
0
0
1
6
1
1
1
1
1
0
0
7
1
1
1
1
1
1
1