© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
1-1
Chapter 1
Overview
1.1
Introducing the SR5650
The SR5650 is the system logic of the latest server/workstation platform from AMD that enables its next generation
CPUs. The SR5650 has a total of 26 PCI Express
®
(PCIe
®
) lanes: 22 lanes are dedicated for external PCIe devices, and 4
are dedicated for the A-Link Express II interface to AMD’s Southbridges such as the SP5100 (formerly SB700S). The
SR5650 also comes equipped with the new HyperTransport™ 3 and PCIe Gen 2 technologies. All of these are achieved
by a highly integrated, thermally efficient design in a 29mm x 29mm package.
The SR5650 introduces a variety of Reliability, Availability and Serviceability (RAS) capabilities. These include parity
protection for on-chip memories, PCI Express Advanced Error Reporting (AER), and advanced error handling
capabilities for HyperTransport.
The SR5650 also supports a revision 1.26 compliant IOMMU (Input/Output Memory Management Unit) implementation
for address translation and protection services. This feature allows virtual addresses from PCI Express endpoint devices to
be translated to physical memory addresses. On-chip caching of address translations is provided to improve I/O
performance. The device is also compliant with revision 1.0 of the PCI Express Address Translation Services (ATS)
specification to enable ATS-compliant endpoint devices to cache address translation. These features enhance memory
protection and support hardware-based I/O virtualization when combined with appropriate operating system or hypervisor
software. Combined with AMD Virtualization™ (AMD-V™) technology, these features are designed to provide
comprehensive platform level virtualization support.
1.2
SR5650 Features
1.2.1 CPU Interface
•
Supports 16-bit up/down HyperTransport™ (HT) 3.0 interface up to 5.2 GT/s.
•
Supports 200, 400, 600, 800, and 1000 MHz HT1 frequencies.
•
Supports 1200, 1400, 1600, 1800, 2000, 2200, 2400, and 2600 MHz HT3 frequencies (up to 2400 MHz only for the
RX980) .
•
Supports “Shanghai” and subsequent series of AMD server/workstation and desktop processors through sockets F,
AM3, G34, and C32.
•
Supports LDTSTOP interface and CPU throttling.
1.2.2 PCI Express
®
Interface
•
Supports PCIe Gen 2 (version 2.0).
•
Optimized peer-to-peer and general purpose link performance.
•
Supports 22 PCIe Gen 2 general purpose lanes, and up to 8 devices on specific ports (possible configurations are
described in
•
Supports a revision 1.26 compliant IOMMU (Input/Output Memory Management Unit) implementation for address
translation and protection services. Please refer to the
AMD I/O Virtualization Technology (IOMMU) Specification
for more details.
1.2.3 A-Link Express II Interface
•
One x4 A-Link Express II interface for connection to an AMD Southbridge. The A-Link Express II is a proprietary
interface developed by AMD based on the PCI Express technology, with additional Northbridge-Southbridge
messaging functionalities.