Interrupt Handling
© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
2-5
2.4.3 Integrated IOAPIC Support
The SR5650 supports routing local INTx messages to its integrated IOAPIC. The integrated IOAPIC contains a 32-entry
redirection table. INTx messages from endpoint devices, bridges, HTIU, and IOMMU can be mapped onto different
redirection entries under register control.
2.4.4 MSI Interrupt Handling and MSI to HT Interrupt Conversion
In MSI interrupt mode, all interrupts are sent directly from the endpoint devices through the SR5650 up to the processor
complex. All MSI interrupts are converted into HT-formatted interrupts. For MSIs from PCI Express endpoint devices
and internally generated PCI Express interrupts, the conversion occurs in the associated IOMMU L1 block. For IOMMU
interrupts and, optionally, HT error interrupts and internal parity error interrupts, the conversion occurs in the HTIU
block. HT error interrupts and internal parity error interrupts may be optionally redirected to an MSI generation block
underneath the SB VC1 IOMMU L1 so that they can be remapped by IOMMU. IOMMU internal MSI interrupts are never
remapped.
The PCI configuration spaces of each on-board device contains a fixed HT MSI mapping capability (except for Device 1,
which is unused). This implies that all MSI interrupts with address 0xFEEx_xxxx have to be converted to HT interrupts.
Because of this, software is required to program all MSI address registers with an 0xFEEx_xxxx address.
2.4.5 Internally Generated Interrupts
The SR5650 may internally generate interrupts for the following purposes:
•
PCI Express error
•
PCI Express PME
•
HT error
•
Internal parity error
•
IOMMU command handler
•
IOMMU event logger
Internally generated interrupts may be in either legacy INTx or MSI format. Internal MSI interrupt sources do not support
per-vector masking.
2.4.6 IOMMU Interrupt Remapping
When the IOMMU is enabled, interrupts generated downstream of the IOMMU are remapped based upon the IOMMU
tables. The following classes of interrupts are not remapped by the IOMMU because they are generated upstream of the
IOMMU:
•
HT error (optional)
•
Internal parity error (optional)
•
IOMMU command handler and event logger
2.4.7 Interrupt Routing Architecture
2.4.7.1 Legacy Mode
Primary SR5650:
Legacy INTx messages are routed directly to the SB IOAPIC. The SB IOAPIC generates upstream
interrupt requests, which are translated by the IOMMU before they are delivered up to the processor complex.
Secondary SR5650:
Legacy INTx messages are routed over HyperTransport through the processor complex to the
primary
SR5650
, which forwards them to the SB IOAPIC. The SB IOAPIC generates upstream interrupt requests, which
are translated by the IOMMU before being delivered up to the processor complex.
The routing paths are illustrated in
below.