© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
List of Tables-1
List of Tables
Table 1-1: Device IDs for the SR5690/5670/5650 Chipset Family
................................................................................................1-3
..............................................................................................................................................................1-4
Table 1-3: Acronyms and Abbreviations
........................................................................................................................................1-4
Table 2-1: SR5650 HyperTransport™ Flow Control Buffers
.........................................................................................................2-3
Table 2-2: Types of Errors Detectable by the SR5650 AER Implementation
..............................................................................2-10
Table 2-3: Types of HyperTransport™ Errors Supported by the SR5650
....................................................................................2-11
Table 2-4: Possible Configurations for the PCI Express® General Purpose Links
......................................................................2-12
Table 3-1: HyperTransport™ Interface
...........................................................................................................................................3-4
Table 3-2: PCI Express® Interface for General Purpose External Devices
....................................................................................3-5
Table 3-3: 1 x 4 Lane A-Link Express II Interface for Southbridge
...............................................................................................3-5
Table 3-4: Miscellaneous PCI Express® Signals
............................................................................................................................3-6
...............................................................................................................................................................3-6
Table 3-6: Power Management Pins
...............................................................................................................................................3-6
........................................................................................................................................................3-7
.....................................................................................................................................................................3-7
...................................................................................................................................................................3-9
Table 3-10: Strap Definitions for the SR5650
..............................................................................................................................3-10
Table 3-11: Strap Definition for STRAP_PCIE_GPP_CFG
.........................................................................................................3-10
Table 4-1: Timing Requirements for PCIe® Differential Clocks (GPP1_REFCLK and GPP3_REFCLK at 100MHz)
...............4-1
Table 4-2: Timing Requirements for HyperTransport™ Reference Clock (100MHz)
...................................................................4-1
Table 4-3: Timing Requirements for OSCIN Reference Clock (14.3181818MHz)
.......................................................................4-2
Table 4-4: Power Rail Groupings for the SR5650
..........................................................................................................................4-2
Table 4-5: SR5650 Power Rail Power-up Sequence
.......................................................................................................................4-3
Table 5-1: Power Rail Maximum and Minimum Voltage Ratings
.................................................................................................5-1
Table 5-2: Power Rail Current Ratings
...........................................................................................................................................5-1
Table 5-1: DC Characteristics for PCIe® Differential Clocks (GPP1_REFCLK and GPP3_REFCLK at 100MHz)
....................5-1
Table 5-3: DC Characteristics for 1.8V GPIO Pads
........................................................................................................................5-2
Table 5-4: DC Characteristics for the HyperTransport™ 100MHz Differential Clock (HT_REFCLK)
.......................................5-2
Table 5-5: SR5650 Thermal Limits
................................................................................................................................................5-2
Table 5-6: SR5650 692-Pin FCBGA Package Physical Dimensions
.............................................................................................5-4
Table 5-7: Recommended Board Solder Reflow Profile - RoHS/Lead-Free Solder
......................................................................5-6
Table 6-1: ACPI States Supported by the SR5650
.........................................................................................................................6-1
Table 7-1: Pins on the Test Interface
..............................................................................................................................................7-1
Table 7-2: Example of an XOR Tree
..............................................................................................................................................7-2
.........................................................................................................................................................7-3
Table 7-4: Truth Table for the VOH/VOL Tree Outputs
................................................................................................................7-5
Table 7-5: SR5650 VOH/VOL Tree
...............................................................................................................................................7-6