HyperTransport™ Interface
© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
2-3
Figure 2-3 SR5650 HyperTransport™ Interface Signals
The SR5650 HyperTransport interface has the following features:
•
HyperTransport 3.0 compliant
•
16-bit and 8-bit link widths supported. Width for each direction of the link is independently controlled.
•
400MT/s to 5.2GT/s link speeds in increments of 400MT/s (up to 2GT/s only for HyperTransport 1 mode)
•
DC-coupled HyperTransport mode only
•
UnitID clumping for x16 PCI Express
®
ports
•
Isochronous flow-control mode for Southbridge audio and IOMMU traffic
•
64-bit address extension support (52-bit physical addressing)
•
Link disconnection with tristate, LS1, and LS2 low-power modes
•
Error retry in HyperTransport 3 mode
•
Full HyperTransport-defined BIST support for both internal and external loopback modes
2.1.2 HyperTransport™ Flow Control Buffers
The SR5650 HTIU implements the following flow control buffers in its receiver:
Table 2-1 SR5650 HyperTransport™ Flow Control Buffers
Flow Control Buffer Type
Posted
Non-Posted
Response
Cmd
16 16
Advertise
63
credits.
Data
16
1
Advertise 63 credits.
ISOC Cmd
0
0
Advertise 63 credits.
ISOC Data
0
0
Advertise 63 credits.
HT_TXCALP
HT_RXCALN
HT_RXCALP
HT_TXCALN
HT_RXCADN
2
2
SR5
650
CP
U
HT_RXCADP
HT_RXCTLN
HT_RXCTLP
HT_RXCLKN
HT_RXCLKP
16
16
HT_TXCADN
2
2
HT_TXCADP
HT_TXCTLN
HT_TXCTLP
HT_TXCLKN
HT_TXCLKP
16
16
2
2
2
2