RAS Features
© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
2-7
2.4.7.3 MSI Mode
For both the primary and secondary
SR5650
s:
MSI interrupt requests are remapped by the IOMMU and sent up to the
processor complex. The routing path is illustrated in
below.
Figure 2-6 Interrupt Routing Path in MSI Mode
2.5
RAS Features
2.5.1
Parity Protection
All memories in SR5650 are parity protected to reduce the possibility of silent data corruption. Multiple parity words are
interleaved to convert burst errors (multiple physically adjacent bits corrupted) into multiple single-bit detectable errors to
increase robustness. The minimum number of interleaved parity words in any on-board memory is 4. All macros contain
test circuitry for software to generate false errors on either the read or write side of the memory for verification of error
handling routines. Error injection circuitry only corrupts parity bits rather than real data bits to avoid data corruption.
2.5.1.1 Parity Protection for IOMMU Cache Memories
All IOMMU cache memories are parity protected. When a parity error is detected, the access from the associated bank is
marked as an automatic miss. The cache line is marked as invalid and may later be overwritten with data from system
memory (which is ECC protected). The error is logged in a status bit and an optional interrupt is generated (either fatal,
non-fatal, or correctable parity error).
2.5.1.2 Parity Protection for Normal Memories
All normal memories are also parity protected. When a parity error is detected, the failure is likely to be fatal as there is no
automatic recovery mechanism and no way for hardware to tag a specific request or operation with the error. The error is
logged in a status bit for later diagnosis and an optional interrupt is generated (either fatal or non-fatal parity error).
2.5.2 SERR_FATAL# and NON_FATAL_CORR# Pins
The SR5650 implements a dedicated pin, DBG_GPIO0/SERR_FATAL#, to signal either a system or a fatal error, which
can be used to signal a BMC for further actions. SERR_FATAL# may be asserted on various error conditions like HT
CPU
SB
PCI-E
Endpoint
Device
IOMMU
HT
PCI-
Express
SR5650
MSI Interrupt from PCI-Express device attached to SR5650
Remapped HT Interrupt
SR5650
PCI-E
Endpoint
Device
CPU