Power Rail Sequence
© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
4-3
4.5.1
Power Up
Figure 4-1 below illustrates the power up sequencing for the various power groups, and Table 4-5
explains the symbols in the figure, as well as the associated requirements.
Figure 4-1 SR5650 Power Rail Power Up Sequence
1.8V
VDD18
1.8V
S0-S2
I/O power for GPIO pads
VDDA18PCIE
1.8V
S0-S2
PCI Express interface 1.8V IO and PLL
power
VDDA18HTPLL
1.8V
S0-S2
HyperTransport interface 1.8V PLL power
Note:
1.
Power rails from the same group are assumed to be generated by the same voltage regulator.
2.
Power rails from different groups but at the same voltage can either be generated by separate regulators or by the same regulators as
long as they comply with the requirements specified in the
SR5690 Motherboard Design Guide.
Table 4-5 SR5650 Power Rail Power-up Sequence
Symbol
Parameter
Requirement
Comment
T10
1.8V rails to VDDHTTX (1.2V)
VDDHTTX ramps after 1.8V rails.
See Note 1.
T11
VDDHTTX (1.2V) to VDDPCIE (1.1V)
VDDPCIE ramps together with or after VDDHTTX
See Note 1 and 2.
T12
VDDHTTX(1.2V) to HT_1.1V rails
HT_1.1V rails ramp together with or after VDDHTTX
See Note 1 and 2.
T13
VDDHTTX(1.2V) to VDDC (1.1V)
VDDC ramps together with or after VDDHTTX
See Note 1 and 2.
Notes:
1.
Power rail A ramps after power rail B means that the voltage of rail A does not exceed that of rail B at any time.
2.
Power rail A ramps together with power rail B means that the two rails are controlled by the same enable signal and the difference
in their ramping rates is only due to the differences in the loadings.
Table 4-4 Power Rail Groupings for the SR5650
Group Name
Power rail name
Voltage
ACPI
STATE
Description
VDDC
HT_1.1V
VDDPCIE
VDDHTTX
1.8V
T10
T11
T12
T13