Integration
0
0
0
t
t
t
1
t Reset
In
t int
t Delay
Out
IEC13000175-2-en.vsd
IEC13000175 V2 EN
Figure 404:
IN pulse length sufficient for integration to reach the set t
Delay
, OUT is
set until the t
Reset
time has elapsed, which resets t
Delay
and OUT
0
0
0
t
t
t
In
Integration
1
t int
t Delay
tReset
Out
IEC13000174=2=en.vsd
IEC13000174 V1 EN
Figure 405:
IN pulse too short for integration to reach the set t
Delay
0
0
0
t
t
t
1
In
Integration
t int
t Delay
Out
t Reset
t Reset
tReset
IEC13000176-2-en.vsd
IEC13000176 V1 EN
Figure 406:
IN pulse too short for integration to reach the set t
Delay
, and t
Reset
resets integration before next pulse can be integrated.
Section 15
1MRK502052-UEN B
Logic
850
Technical manual
Содержание Relion REG670
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