ABB Relion REG670, Техническое руководство

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new start-up is also required, for example, after maintenance of the auxiliary voltage
system.
When the time difference is >16μs, the differential function is blocked and the time
regulator for the hardware clock automatically uses a fast mode to synchronize the
clock systems. The time adjustment is made with an exponential function, that is, with
big time adjustment steps in the beginning, and then smaller steps until a time
deviation between the GPS time and the differential time system of <16μs has been
reached. The differential function is then enabled and the synchronization remains in
fast mode or switches to slow mode depending on the setting.
Slow clock synchronization mode
During normal service, a setting with slow synchronization mode is used. This
prevents the hardware clock to make too big time steps, >16µs, emanating from the
differential protection requirement of correct timing.
Synchronization principle
From a general point of view synchronization can be seen as a hierarchical structure.
A function is synchronized from a higher level and provides synchronization to lower
levels.
Function
Synchronization from
a higher level
Optional synchronization of
modules at a lower level
IEC09000342-1-en.vsd
IEC09000342 V1 EN
Figure 503: Synchronization principle
A function is said to be synchronized when it periodically receives synchronization
messages from a higher level. As the level decreases, the accuracy of the
synchronization decreases as well. A function can have several potential sources of
synchronization, with different maximum errors. This gives the function the
possibility to choose the source with the best quality, and to adjust its internal clock
based on this source. The maximum error of a clock can be defined as:
• The maximum error of the last used synchronization message
• The time since the last used synchronization message
• The rate accuracy of the internal clock in the function.
Section 20
1MRK502052-UEN B
Basic IED functions
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Technical manual