Technical Data
Block diagrams
240
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ERR
BUS
PWR
µC
Supply
µC
+
1
–
3
+
2
–
4
V1
V2
+
1
–
3
+
2
–
4
V1
V2
X1
X2
IN/OUT
Diag
V1 Diag
V2 Diag
P2
P1
ETH2
ETH1
Ethernet
Ethernet
V1 +
Diag
IN
2 AI +
1 V
AUX
1
3 GND
4 AI –
I/V differential common
4AI
5 FE
AI +
V
AUX
1
AI –/GND
n.c.
FE
V1 +
V2 +
D/A
Filter
PGA
Diag
IN
2 R +
1 RL +
3 RL –
4 R –
PT
4AI
5 FE
V1 +
D/A
Filter
PGA
Diag
IN
2 AI +
1 CJC +
3 CJC –
4 AI –
TC
4AI
5 FE
V1 +
D/A
Filter
PGA
V2 +
Diag
2 AO +
1 V2 +
3 GND
4 AO –
I/V
4AO
5 FE
Out
D
A
1
3
2
4
1
3
2
4
Fig. 86: Block diagram – analog modules
