V04.00 | 2021/05
55
TBEN-S1-8DXP
Word no.
Bit no.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Control
0x0000
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Outputs
0x0001
-
-
-
-
-
-
-
-
DX7 DX6 DX5 DX4 DX3
DX2
DX1
DX0
Latch reset
0x0002
-
-
-
-
-
-
-
-
DX7 DX6 DX5 DX4 DX3
DX2
DX1
DX0
Counter reset
0x0003
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CNT_
Reset
PWM ch3
0x0004
-
-
-
-
-
-
-
-
Duty Cycle
PWM ch7
0x0005
-
-
-
-
-
-
-
-
Duty Cycle
TBEN-S2-8DXP
Word no.
Bit no.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Control
0x0000
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Outputs
0x0001
-
-
-
-
-
-
-
-
DX7 DX6 DX5 DX4 DX3
DX2
DX1
DX0
Latch reset
0x0002
-
-
-
-
-
-
-
-
DX7 DX6 DX5 DX4 DX3
DX2
DX1
DX0
Counter reset
0x0003
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CNT_
Reset
PWM ch3
0x0004
-
-
-
-
-
-
-
-
Duty Cycle
PWM ch7
0x0005
-
-
-
-
-
-
-
-
Duty Cycle
VAUX Control
0x0006
-
-
-
-
-
-
-
-
-
-
-
-
VAUX2
P1 C3
VAUX2
P1 C2
VAUX1
P1 C1
VAUX1
P1 C0
Meaning of the process data bits
Name
Meaning
I/O data
DIx
Latch reset bit for input channels
DOx
Output bit
DXx
Output bit of DXP channel
DXx
Latch reset bit for DXP channels