Siemens ERTEC 200P, Manual

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Copyright © Siemens AG 2016. All rights reserved 12 ERTEC 200P-2 Manual
Technical data subject to change Version 1.0
List of Figures
Figure 1: ERTEC 200P use cases 19
Figure 2: Application operation with external host 20
Figure 3: Application operation without external host 21
Figure 4: ERTEC 200P Step2 block diagram 24
Figure 5: ARM926 subsystem 26
Figure 6: JTAG chain 31
Figure 7: AHB/APB bridge, block diagram 49
Figure 8: APB bridge, timing 50
Figure 9: EMC Block Diagram 158
Figure 10: EMC interface with two SDRAM / two Burst Flash configuration 159
Figure 11: EMC interface with only one SDRAM / one Burst Flash configuration 160
Figure 12: EMC interface with asynchronous RAM 160
Figure 13: EMC, Address Space 161
Figure 14: EMC, Notation definition for a read access (ASYNC) 164
Figure 15: EMC, Notation definition for a write access (ASYNC) 165
Figure 16: EMC, Application Example SDRAM 166
Figure 17: EMC, Application example: Combination of SDRAM and asynchronous
Interfaces
166
Figure 18: EMC, Interface Signals 167
Figure 19: Block diagram of the host interface 182
Figure 20: XHIF, Symbol and Signals 184
Figure 21: XHIF interface adjustment 186
Figure 22: Block diagram of the peripheral interface 198
Figure 23: Block diagram of PN-ICU for PN_IRQx(0/1:0) group interrupts 231
Figure 24: Block diagram of PN-MUX for PN_IRQx(2:1/15:2) single interrupts 232
Figure 25: PNPLL with 3 application time blocks (application connection) 233
Figure 26: Quartz wiring 237
Figure 27: Clock source for the Ethernet connection 238
Figure 28: ERTEC 200P reset matrix 242
Figure 29: PLL startup phase 243
Figure 30: Block diagram of the IO filter 248
Figure 31: Block diagram of the filter structure of a channel 248
Figure 32: Block diagram of the central clock divider 249
Figure 33: Signal in signal filtering 251
Figure 34: Block diagram ARM926 Watchdog 260
Figure 35: XWD_OUT0/ WD_INT signal sequence 263
Figure 36: XWD_OUT1 signal sequence 264
Figure 37:TIMER block diagram 273
Figure 38: F-timer block diagram 303
Figure 39: Baud rates UART when F
UARTCLK
= 125 MHz 307
Figure 40: SPI Block Diagram 340
Figure 41: SPI flash: serial output timing 343
Figure 42: SPI flash: serial input timing 343
Figure 43: Block diagram of a GPIO module 350
Figure 44: GPIO, IO Circuit 352