Copyright © Siemens AG 2016. All rights reserved
30
ERTEC 200P-2 Manual
Technical data subject to change
Version 1.0
2.3.1.3.4 Bus Interface of the ARM926 Processor
The ARM926 processor has separate AHB interfaces for opcode fetches (ARM926-I) and
data transfers (ARM926-D). The interfaces operate at 125 MHz. The data bus width and
address bus width are each 32 bits. The data bus interfaces operate over a write buffer
(16-stage FIFO). When the write buffer is used, data write sequences are transferred to
the write buffer and the data unit of the processor can continue processing immediately.
More information on the bus interface and the write buffer can be found in /7/ (see chap-
ter 7.2.)
2.3.1.3.5 ARM926 Embedded Trace Macrocell (ETM9), Trace Buffer (ETB11)
To support debugging, an ETM9 revision r2p2 (
F
) module with integrated trace
buffer (ETB11) is connected to the ARM926EJ-S system in the ERTEC 200P. This mod-
ule allows an instruction and data trace. The trace buffer is 2Kx32 bits and supports both
ARM926 clocks (125 / 250 MHz).
Alongside the integrated trace buffer, an external ARM926 trace port at the XHIF port is
also available as an alternative function for
ARM926 operation at 125 MHz
. The
ARM926 trace port is enabled with the configuration pins (CONFIG(6..3) = 1110b, see
2.3.10.9.3
X
).
The ETM module receives all signals required for the data and instruction trace from the
processor. The ETM9 module is operated over the JTAG interface. The trace information
is output at the trace port over a FIFO or entered in the internal trace buffer. In normal
mode (not multiplexed or demultiplexed mode), the trace port is operated with a width of
4, 8 or 16 data bits. TRACEPKT outputs of the trace port at GPIO53-38 (when
CONFIG6:3 = 1110, see 2.3.10.8.4.1) that are not used by the debugger remain high-
impedance.
Only the half-rate mode is supported as clock mode. The trace clock runs at half the
processor frequency (62.5 MHz with a processor clock of 125 MHz) and the trace data
have a maximum change frequency of 125 MHz. The debugger accepts the data with
both trace clock edges. Standard Lauterbach or Hitex debuggers support trace clock
frequencies of up to 200 MHz.
The trace buffer (ETB11) is connected to the AHB and could be employed for normal
rapid data storage if not used. However, as an external connection to the module is re-
quired for the XTRST pin (see note on the JTAG interface in 0), AHB access to the ETM
trace buffer SRAM is not possible during operation.
Recording in the trace buffer can be controlled by the external debugger over the JTAG
interface or by the SW on the ARM926EJ-S
F
. A register set that can also be accessed
from the AHB is available in ETB11 for this purpose. ARM926EJ-S has two interrupts for
processing the trace (ETB_ACQCOMP -> Required trace is saved in the ETB;
ETB_FULL -> Trace overrun in the ETB) (see 2.3.2.14
). The trace can, however, only be
read from the trace buffer once tracing is complete (ETB_ACQCOMP interrupt).
Recording in the internal trace buffer can be suppressed when an external trace port is
used.
3
The ETM9 cell has a larger FIFO (18 -> 45 bytes).
4
ETM trace condition configuration is only possible from the external debugger and not over the AHB
interface of the ETB11.
