Copyright © Siemens AG 2016. All rights reserved
22
ERTEC 200P-2 Manual
Technical data subject to change
Version 1.0
1.4.2 EMC Burst Flash Interface
The EMC of the ERTEC 200P has two possible settings for clocked signal output
(XAV_BF) to external burst flash. These can be configured over
EXTENDED_CONFIG.BFODM
EXTENDED_CONFIG.BFODM
= ’0’:
Burst flash signal output with feedback
clock at pin
CLK_I_BF
(register value after reset)
EXTENDED_CONFIG.BFODM
=
’1’
: Burst Flash signal output with internal
system clock
(value required for correct operation!)
The EMC of the ERTEC 200P has two possible settings for selecting the operating
frequency of externally connected burst flash. These can be configured over
BF_CONFIG.BF_CLK_F
(see chapter 2.3.5.8):
BF_CONFIG.BF_CLK_F
=
’0’
: Half-rate BF, 62.5 MHz
(register value after reset)
BF_CONFIG.BF_CLK_F
=
’1’: Full rate BF, 125 MHz
(value is not supported in ERTEC 200P !)
Note:
The timing specifications for the ERTEC 200P board layout only apply for the above
settings.
1.4.3 No free-running frequency at quartz break
To detect a quartz break, the LOSS signal is generated with the output frequency (in
this case the free-running frequency) of the PLL (see chapter 4.4) to allow, for exam-
ple, the F-timer to run and this event to be detected even following a quartz break, the
PLL must continue to provide a free-running frequency despite the absence of a quartz
clock (i.e. CLKP_A open or clamped at '1' or '0'). This free-running frequency must be:
< 500 MHz
AND
> 4 x 32 kHz
(according to specifications: 350 MHz)
Background:
With the PLL used in ERTEC 200P, only the CLK output (CLKOA) generates a free-
running frequency; the outputs CLKOB and CLKOC do not. As multiplication (factor of
20) of the quartz clock (25 MHz) to 500 MHz is only possible at the CLKOB output (a
To achieve the correct timing, configure EXTENDED_CONFIG.BFODM = '1'.
EXTENDED_CONFIG.BFODM = '0' (default value) is not permitted.
To achieve the correct timing, configure / retain BF_CONFIG.BF_CLK_F = '0'
(default value). BF_CONFIG.BF_CLK_F = '1' is not permitted.
With the current PLL design, this is not the case. When there is no quartz clock, the
PLL returns a free-running frequency of 0 Hz.
