Copyright © Siemens AG 2016. All rights reserved
240
ERTEC 200P-2 Manual
Technical data subject to change
Version
1.0
Note:
Evaluation of the LOSS mechanism by the FW is guaranteed as PLL free-running frequency (100MHz
– 300MHz) < PLL operating frequency (500 MHz).
The LOCK signals:
The generation of the LOCK signals is disabled as long as the Lock-Monitor is
disabled (i.e. XRESET = 0).
The core of the LOCK logic are a count up counter that increment with the output
frequencies (500MHz) of the PLL. With each rising edge of the oscillator output:
o
the value of the counter are checked against the limits (+/- 15%) compared to
the nominal value (< 425MHz or > 575MHz) for LOCK signal is inactiv
o
the value of the counter are checked against the limits (+/- 10%) compared to
the nominal value (> 450MHz and < 550MHz) for LOCK signal is activ
o
The counter are reset to zero.
The LOCK signal is active if the ratio between the oscillator frequency and the
output frequencies of the PLLs are within the limits (+/- 10%) for more than three
oscillator periods.
The LOCK signal is inactive, if the ratio between the oscillator frequency and the
output frequencies of the PLLs are outside the limits (+/- 15%) for more than three
oscillator periods.
Note that “three oscillator periods” means an integral action.
Note:
If the deviation from the PLL output frequency is caused by the wrong oscillator input
frequency, i.e. an oscillator input frequency that does not correspond to the rated
value (25 MHz), this cannot be detected by the LOCK monitor because the PLL has
already adjusted to the new output frequency during easurement (3 oscillator clocks)
in line with the specified frequency (20).
