Copyright © Siemens AG 2016. All rights reserved
415
ERTEC 200P-2 Manual
Technical data subject to change
Version 1.0
2.4 Memory Mapping
2.4.1 Memory Mapping ARM926-I
Seg
Address-Range
Memory/
Peripheral
Size /Byte
Description
0
0x0
000_0000h
...
0x0
000_1FFFh
0x0
3FF_FFFFh
Boot ROM (8 KByte)
EMC (64 MByte)
8 KByte
64 MByte
MEM_SWAP parameter assignment:
00b: -> Boot ROM (0 - 8 KByte), imaged
F
01b: -> EMC SDRAM (0 - 64 MByte)
10b: -> EMC asyn memory (0 - 64 MByte)
11b: -> QVZ Error
ARM926 I-TCM (0 – 256 KByte / Step 64
KByte)
F
0x0
400_0000h
...
0x0
FFF_FFFFh
Not used
192 MByte
1
0x1
000_0000h
...
0x1
FFF_FFFFh
Not used
256 MByte
2
0x2
000_0000h
...
0x2
FFF_FFFFh
EMC SDRAM
256 MByte
3
0x3
000_0000h
...
0x3
FFF_FFFFh
EMC Asyn
Memory
256 MByte
0x4
000_0000h
...
0x4
000_7FFFh
Not used
32 KByte
0x4
000_8000h
...
0x4
000_9FFFh
Boot ROM
8 KByte
0x4
000_A000h
...
0x4
FFF_FFFFh
Not used
< 256 MByte
5-F
0x5
000_0000h
...
0XF
FFF_FFFFh
Not used
2816 MByte
7
After a reset, the boot ROM is at address 0. The first 64 MByte of EMC-SDRAM or EMC asyn memory (chip select
Bank0) can also be mapped to address 0 with the MEM_SWAP register in the SCRB (see 2.3.10.9.22).
8
The ARM926 I-TCM is 0 - 256 KByte (adjustable in 64 KByte increments) and can be displayed by the SW in the
ARM926 coprocessor register CP15 c9 at address 0 or at another address in segment 0 (except in the D-TCM926 / D-
TCM966 range). The I-TCM is disabled after reset. After display, ARM926 accesses its I-TCM and not the AHB in this
address range (ARM926 cannot access its I-TCM over the AHB). Please note that ARM926 I-TCM can only be dis-
played in the ARM address range in increments of 2
n
. If, for example, a physical size of I-TCM = 192 KByte has been
selected in 'TCM926_Map Register', ARM926 can only assign I-TCM an address range of 256 KByte.