Copyright © Siemens AG 2016. All rights reserved
461
ERTEC 200P-2 Manual
Technical data subject to change
Version
1.0
3.3.2.1.2
Common RD/WR
The following figure shows the timing, when the External Host initiates a
Common Read
Access
.
Parameter Description
Min
Max
t
RCS
Write signal deasserted to chip select as-
serted delay
6.2 ns
t
ACS
address valid to chip select asserted setup
time
2.1 ns
t
CRT
chip select asserted to ready deasserted
delay
2.8 ns
11.7 ns
t
CDE
chip select asserted to data enable delay
2.5 ns
11.9 ns
t
RAP
ready active pulse width
6.1 ns
10.2 ns
t
RTD
ready asserted to data valid delay
10.6 ns
t
CWH
chip select deasserted to write signal assert-
ed delay
0.9 ns
t
CAH
address valid to chip select deasserted hold
time
1.2 ns
t
RDH
data valid/enable to chip select deasserted
hold time
2.5 ns
11.7 ns
t
RR
read recovery time
8.8 ns
Based on
Tc = 8 ns (AHB Clock = 125 MHz);
Load-value for Timing = 20pF
Buffer Driverstrength = 9mA
IO-Voltage = 3,3V
