NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
90 / 183
Table 87. TPM1C0SC register field descriptions
Field
Description
7
CH0F
Channel 0 Flag — When channel n is configured for input capture, this flag bit is set when an active edge
occurs on the channel n pin. When channel 0 is an output compare or edge-aligned PWM channel, CH0F is
set when the value in the TPM1 counter registers matches the value in the TPM1 channel 0 value registers.
This flag is seldom used with center-aligned PWMs because it is set every time the counter matches the
channel value register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CH0F is set and interrupts are enabled (CH0IE = 1). Clear
CH0F by reading TPM1C0SC while CH0F is set and then writing a 0 to CH0F. If another interrupt request
occurs before the clearing sequence is complete, the sequence is reset so CH0F would remain set after the
clear sequence was completed for the earlier CH0F. This is done so a CH0F interrupt request cannot be
lost by clearing a previous CH0F. Reset clears CH0F. Writing a 1 to CH0F has no effect.
0 No input capture or output compare event occurred on channel 0
1 Input capture or output compare event occurred on channel 0
6
CH0IE
Channel 0 Interrupt Enable — This read/write bit enables interrupts from channel 0. Reset clears CH0IE.
0 Channel 0 interrupt requests disabled (use software polling)
1 Channel 0 interrupt requests enabled
5
MS0B
Mode Select B for TPM1 Channel 0 — When CPWMS = 0, MS0B = 1 configures TPM1 channel 0 for edge-
aligned PWM mode. For a summary of channel mode and setup controls, refer to
Table 88
.
4
MS0A
Mode Select A for TPM1 Channel 0 — When CPWMS = 0 and MS0B = 0, MS0A configures TPM1 channel
0 for input capture mode or output compare mode. Refer to
Table 88
for a summary of channel mode and
setup controls.
3:2
ELS0[B:A]
Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by
CPWMS:MS0B:MSnA and shown in
Table 88
, these bits select the polarity of the input edge that triggers
an input capture event, select the level that will be driven in response to an output compare match, or select
the polarity of the PWM output. Setting ELS0B:ELS0A to 0:0 configures the related timer pin as a general-
purpose I/O pin unrelated to any timer channel functions. This function is typically used to temporarily
disable an input capture channel or to make the timer pin available as a general-purpose I/O pin when the
associated timer channel is set up as a software timer that does not require the use of a pin.
Table 88. Mode, edge, and level selection
CPWMS
MS0B:MS0A
ELS0B:ELS0A
Mode
Configuration
X
XX
00
Pin not used for TPM1 channel; use as an external clock for the
TPM1 or revert to general-purpose I/O
01
Capture on rising edge only
10
Capture on falling edge only
00
11
Input capture
Capture on rising or falling edge
00
Software compare only
01
Toggle output on compare
10
Clear output on compare
01
11
Output compare
Set output on compare
10
High-true pulses (clear output on compare)
0
1x
x1
Edge-
aligned PWM Low-true pulses (set output on compare)
10
High-true pulses (clear output on compare-up)
1
XX
x1
Center-
aligned PWM Low-true pulses (set output on compare-up)
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