NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
83 / 183
Bit-Manipulation
Branch
Read-Modify-Write
Control
Register/Memory
05 5
BRCLR2
3
DIR
15 5
BCLR2
2
DIR
25 3
BCS
2
rel
35 4
STHX
2
DIR
45 3
LDHX
3
IMM
55 4
LDHX
2
DIR
65 3
CPHX
3
IMM
75 5
CPHX
2
DIR
85 1
TPA
1
INH
95 2
TSX
1
INH
A5 2
BIT
2
IMM
B5 3
BIT
2
DIR
C5 4
BIT
3
EXT
D5 4
BIT
3 IX2
E5 3
BIT
2 IX1
F5 3
BIT
1 IX
06 5
BRSET3
3
DIR
16 5
BSET3
2
DIR
26 3
BNE
2
rel
36 5
ROR
2
DIR
46 1
RORA
1
INH
56 1
RORX
1
INH
66 5
ROR
2 IX1
76 4
ROR
1 IX
86 3
PULA
1
INH
96 5
STHX
3 EXT
A6 2
LDA
2
IMM
B6 3
LDA
2
DIR
C6 4
LDA
3
EXT
D6 4
LDA
3 IX2
E6 3
LDA
2 IX1
F6 3
LDA
1 IX
07 5
BRCLR3
3
DIR
17 5
BCLR3
2
DIR
27 3
BEQ
2
rel
37 5
ASR
2
DIR
47 1
ASRA
1
INH
57 1
ASRX
1
INH
67 5
ASR
2 IX1
77 4
ASR
1 IX
87 2
PSHA
1
INH
97 1
TAX
1
INH
A7 2
AIS
2
IMM
B7 3
STA
2
DIR
C7 4
STA
3
EXT
D7 4
STA
3 IX2
E7 3
STA
2 IX1
F7 2
STA
1 IX
08 5
BRSET4
3
DIR
18 5
BSET4
2
DIR
28 3
BHCC
2
rel
38 5
LSL
2
DIR
48 1
LSLA
1
INH
58 1
LSLX
1
INH
68 5
LSL
2 IX1
78 4
LSL
1 IX
88 3
PULX
1
INH
98 1
CLC
1
INH
A8 2
EOR
2
IMM
B8 3
EOR
2
DIR
C8 4
EOR
3
EXT
D8 4
EOR
3 IX2
E8 3
EOR
2 IX1
F8 3
EOR
1 IX
09 5
BRCLR4
3
DIR
19 5
BCLR4
2
DIR
29 3
BHCS
2
rel
39 5
ROL
2
DIR
49 1
ROLA
1
INH
59 1
ROLX
1
INH
69 5
ROL
2 IX1
79 4
ROL
1 IX
89 2
PSHX
1
INH
99 1
SEC
1
INH
A9 2
ADC
2
IMM
B9 3
ADC
2
DIR
C9 4
ADC
3
EXT
D9 4
ADC
3 IX2
E9 3
ADC
2 IX1
F9 3
ADC
1 IX
0A 5
BRSET5
3
DIR
1A 5
BSET5
2
DIR
2A 3
BPL
2
rel
3A 5
DEC
2
DIR
4A 1
DECA
1
INH
5A 1
DECX
1
INH
6A 5
DEC
2 IX1
7A 4
DEC
1 IX
8A 3
PULH
1
INH
9A 1
CLI
1
INH
AA 2
ORA
2
IMM
BA 3
ORA
2
DIR
CA 4
ORA
3
EXT
DA 4
ORA
3 IX2
EA 3
ORA
2 IX1
FA 3
ORA
1 IX
0B 5
BRCLR5
3
DIR
1B 5
BCLR5
2
DIR
2B 3
BMI
2
rel
3B 7
DBNZ
3
DIR
4B 4
DBNZA
2
INH
5B 4
DBNZX
2
INH
6B 7
DBNZ
3 IX1
7B 6
DBNZ
2 IX
8B 2
PSHH
1
INH
9B 1
SEI
1
INH
AB 2
ADD
2
IMM
BB 3
ADD
2
DIR
CB 4
ADD
3
EXT
DB 4
ADD
3 IX2
EB 3
ADD
2 IX1
FB 3
ADD
1 IX
0C 5
BRSET6
3
DIR
1C 5
BSET6
2
DIR
2C 3
BMC
2
rel
3C 5
INC
2
DIR
4C 1
INCA
1
INH
5C 1
INCX
1
INH
6C 5
INC
2 IX1
7C 4
INC
1 IX
8C 1
CLRH
1
INH
9C 1
RSP
1
INH
BC 3
JMP
2
DIR
CC 4
JMP
3
EXT
DC 4
JMP
3 IX2
EC 3
JMP
2 IX1
FC 3
JMP
1 IX
0D 5
BRCLR6
3
DIR
1D 5
BCLR6
2
DIR
2D 3
BMS
2
rel
3D 4
TST
2
DIR
4D 1
TSTA
1
INH
5D 1
TSTX
1
INH
6D 4
TST
2 IX1
7D 3
TST
1 IX
9D 1
NOP
1
INH
AD 5
BSR
2
rel
BD 5
JSR
2
DIR
CD 6
JSR
3
EXT
DD 6
JSR
3 IX2
ED 5
JSR
2 IX1
FD 5
JSR
1 IX
0E 5
BRSET7
3
DIR
1E 5
BSET7
2
DIR
2E 3
BIL
2
rel
3E 6
CPHX
3 EXT
4E 5
MOV
3 DD
5E 5
MOV
2
DIX+
6E 4
MOV
3
IMD
7E 5
MOV
2
IX+D
8E
2+
STOP
1
INH
9E
Page
2
AE 2
LDX
2
IMM
BE 3
LDX
2
DIR
CE 4
LDX
3
EXT
DE 4
LDX
3 IX2
EE 3
LDX
2 IX1
FE 3
LDX
1 IX
0F 5
BRCLR7
3
DIR
1F 5
BCLR7
2
DIR
2F 3
BIH
2
rel
3F 5
CLR
2
DIR
4F 1
CLRA
1
INH
5F 1
CLRX
1
INH
6F 5
CLR
2 IX1
7F 4
CLR
1 IX
8F
2+
WAIT
1
INH
9F 1
TXA
1
INH
AF 2
AIX
2
IMM
BF 3
STX
2
DIR
CF 4
STX
3
EXT
DF 4
STX
3 IX2
EF 3
STX
2 IX1
FF 2
STX
1 IX
INH
Inherent
rel
relative
SP1
Stack Pointer, 8-Bit Offset
IMM
Immediate
IX
Indexed, no offset
SP2
Stack Pointer, 16-Bit offset
DIR
Direct
IX1
Indexed, 8-Bit offset
IX+
Indexed, No offset with post increment
EXT
Extended
IX2
Indexed, 16-Bit offset
IX1+
Indexed, 1-Byte offset with post increment
DD
DIR to DIR
IMD
IMM to DIR
IX+D
IX+ to DIR
DIX+
DIR to IX+
Opcode in Hexadecimal
Number of Bytes
F0 3
SUB
1 IX
HCS08 Cycles
Instruction Mnemonic
Addressing Mode
Table 77. Opcode map (Sheet 2 of 2)
Bit-Manipulation
Branch
Read-Modify-Write
Control
Register/Memory
9E60 6
NEG
3
SP1
9ED0
5
SUB
4
SP2
9EE0
4
SUB
3
SP1
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