NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
143 / 183
aaa-028038
low
bit
low
bit
FSK = f
RF
+ f
FSK = f
RF
- f
OOK = f
RF
OOK = OFF
bit time
Consecutive “0
data bits
Consecutive “1
data bits
“001101
data bits
bit time
high
bit
bit time
high
bit
bit time
Figure 45. Bi-Phase data bit encoding (POL = 1)
15.6 RF output stage
The RF output stage consists of a PLL, control logic and an output RF amplifier. Data is
sent to the RF output stage from either the RF data buffer or the DATA bit in the RFCR3
depending on the selected mode of operation as described in
Section 15.1 "RF data
modes"
.
The RF output stage is enabled by the state of the SEND control bit. The PLL in the RF
output stage will signal back via the RCTS status bit when the PLL is locked and ready to
transmit.
15.6.1 Modulation method
The modulation control bit, MOD, described in
Section 15.18 "PLL control registers B -
PLLCR[3:2], RPAGE = 0"
, sets the modulation of the RF signal will be either amplitude
shift keying (OOK) or frequency shift keying (FSK) with several options for the frequency
shift.
When operating in the FSK mode the internal, fractional-n PLL divider will be used to
create the two carrier frequencies for data zero and data one. This method is more
effective and robust than "pulling" the external crystal in order to shift the carrier
frequency.
15.6.2 Carrier frequency
The carrier frequency is established mainly by the external crystal used, but a centering
of the fractional-n PLL provides more precise control. If the CF control bit is clear the PLL
will be configured for a carrier center frequency of the 315 MHz. If the CF control bit is set
the PLL will be configured for a carrier center frequency of the 434 MHz.
15.6.3 RF power output
The maximum power output from the RF pin can be adjusted to one of 21 levels using
the PWR[4:0] bits.
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