NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
96 / 183
for input capture or output compare functions. The period of this PWM signal is
determined by the setting in the modulus register (TPM1MODH:TPM1MODL).
The duty cycle is determined by the setting in the timer channel value register
(TPM1CnVH:TPM1CnVL). The polarity of this PWM signal is determined by the setting in
the ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible.
As
Figure 19
shows, the output compare value in the TPM1 channel registers determines
the pulse width (duty cycle) of the PWM signal. The time between the modulus overflow
and the output compare is the pulse width. If ELSnA = 0, the counter overflow forces the
PWM signal high and the output compare forces the PWM signal low. If ELSnA = 1, the
counter overflow forces the PWM signal low and the output compare forces the PWM
signal high.
aaa-028013
Period
Pulse
width
Overflow
Overflow
Overflow
Output
compare
Output
compare
Output
compare
Figure 19. PWM period and pulse width (ELSnA = 0)
When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting
the timer channel value register (TPMCnVH:TPMCnVL) to a value greater than the
modulus setting, 100% duty cycle can be achieved. This implies that the modulus setting
must be less than 0xFFFF to get 100% duty cycle.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers
are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse
widths. Writes to either register, TPM1CnVH or TPM1CnVL, write to buffer registers. In
edge-PWM mode, values are transferred to the corresponding timer channel registers
only after both 8-bit bytes of a 16-bit register have been written and the value in the
1TPMCNTH:TPM1CNTL counter is 0x0000. (The new duty cycle does not take effect
until the next full period.)
11.5.3 Center-aligned PWM mode
This type of PWM output uses the up-/down-counting mode of the timer counter
(CPWMS = 1). The output compare value in TPM1CnVH:TPM1CnVL determines the
pulse width (duty cycle) of the PWM signal and the period is determined by the value
in TPM1MODH:TPM1MODL. TPM1MODH:TPM1MODL should be kept in the range of
0x0001 to 0x7FFF because values outside this range can produce ambiguous results.
ELS0A will determine the polarity of the CPWM output.
pulse width = 2 x (TPM1CnVH:TPM1CnVL)
period = 2 x (TPM1MODH:TPM1MODL);
for TPM1MODH:TPM1MODL = 0x0001–0x7FFF
If the channel value register TPM1CnVH:TPM1CnVL is zero or negative (bit 15 set), the
duty cycle will be 0%. If TPM1CnVH:TPM1CnVL is a positive value (bit 15 clear) and
is greater than the (nonzero) modulus setting, the duty cycle will be 100% because the
duty cycle compare will never occur. This implies the usable range of periods set by the
modulus register is 0x0001 through 0x7FFE (0x7FFF if generation of 100% duty cycle is
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