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NXP Semiconductors

FXTH87E

FXTH87E, Family of Tire Pressure Monitor Sensors

FXTH87ERM

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Reference manual

Rev. 5.0 — 4 February 2019

171 / 183

Field

Description

FTS

Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches

the BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT

instruction queue, the CPU enters ACTIVE BACKGROUND mode rather than executing the tagged opcode.
0 Tag opcode at breakpoint address and enter ACTIVE BACKGROUND mode if CPU attempts to execute

that instruction
1 Breakpoint match forces ACTIVE BACKGROUND mode at next instruction boundary (address need not

be an opcode)

CLKSW

Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC

clock source.
0 Alternate BDC clock source
1 MCU bus clock

WAIT or STOP Status — When the target CPU is in WAIT or STOP mode, most BDC commands cannot

function. However, the BACKGROUND command can be used to force the target CPU out of WAIT or STOP

and into ACTIVE BACKGROUND mode where all BDC commands work. Whenever the host forces the

target MCU into ACTIVE BACKGROUND mode, the host should issue a READ_STATUS command to check

that BDMACT = 1 before attempting other BDC commands.
0 Target CPU is running user application code or in ACTIVE BACKGROUND mode (was not in WAIT or

STOP mode when BACKGROUND became active)
1 Target CPU is in WAIT or STOP mode, or a BACKGROUND command was used to change from WAIT or

STOP to ACTIVE BACKGROUND mode

WSF

WAIT or STOP Failure Status — This status bit is set if a memory access command failed due to the target

CPU executing a WAIT or STOP instruction at or about the same time. The usual recovery strategy is to

issue a BACKGROUND command to get out of WAIT or STOP mode into ACTIVE BACKGROUND mode,

repeat the command that failed, then return to the user program. (Typically, the host would restore CPU

registers and stack values and re-execute the WAIT or STOP instruction.)
0 Memory access did not conflict with a WAIT or STOP instruction
1 Memory access command failed because the CPU entered WAIT or STOP mode

DVF

Data Valid Failure Status — This status bit is not used in the MC9S08RA16 because it does not have any

slow access memory.
0 Memory access did not conflict with a slow memory access
1 Memory access command failed because CPU was not finished with a slow memory access

17.3.3 BDC breakpoint match register (BDCBKPT)

This 16-bit register holds the address for the hardware breakpoint in the BDC. The

BKPTEN and FTS control bits in BDCSCR are used to enable and configure the

breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT)

are used to read and write the BDCBKPT register but is not accessible to user programs

because it is not located in the normal memory map of the MCU. Breakpoints are

normally set while the target MCU is in ACTIVE BACKGROUND mode before running

the user application program. For additional information about setup and use of

the hardware breakpoint logic in the BDC, refer to

Section 17.2.4 "BDC hardware

breakpoint"

17.3.4 System background debug force reset register (SBDFR)

This register contains a single write-only control bit. A serial BACKGROUND mode

command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this

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