NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
67 / 183
located. This is faster and more memory efficient than specifying a complete 16-bit
address for the operand.
10.4.5 Extended addressing mode (EXT)
In extended addressing mode, the full 16-bit address of the operand is located in the next
two bytes of program memory after the opcode (high byte first).
10.4.6 Indexed addressing mode
Indexed addressing mode has seven variations including five that use the 16-bit H:X
index register pair and two that use the stack pointer as the base reference.
10.4.6.1 Indexed, No Offset (IX)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair
as the address of the operand needed to complete the instruction.
10.4.6.2 Indexed, No Offset with Post Increment (IX+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair
as the address of the operand needed to complete the instruction. The index register
pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This
addressing mode is only used for MOV and CBEQ instructions.
10.4.6.3 Indexed, 8-Bit Offset (IX1)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair
plus an unsigned 8-bit offset included in the instruction as the address of the operand
needed to complete the instruction.
10.4.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair
plus an unsigned 8-bit offset included in the instruction as the address of the operand
needed to complete the instruction. The index register pair is then incremented (H:X =
H:X + 0x0001) after the operand has been fetched. This addressing mode is used only
for the CBEQ instruction.
10.4.6.5 Indexed, 16-Bit Offset (IX2)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair
plus a 16-bit offset included in the instruction as the address of the operand needed to
complete the instruction.
10.4.6.6 SP-Relative, 8-Bit Offset (SP1)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus
an unsigned 8-bit offset included in the instruction as the address of the operand needed
to complete the instruction.
10.4.6.7 SP-Relative, 16-Bit Offset (SP2)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a
16-bit offset included in the instruction as the address of the operand needed to complete
the instruction.
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
