NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
88 / 183
Field
Description
4:3
CLKS[B:A]
Clock Source Select — As shown in
Table 78
, this 2-bit field is used to disable the TPM1 system or select
one of three clock sources to drive the counter prescaler. The internal DX source is synchronized to the bus
clock by an on-chip synchronization circuit.
2:0
PS[2:0]
Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM1 clock input as shown
in
Table 81
. This prescaler is located after any clock source synchronization or clock source selection, so it
affects whatever clock source is selected to drive the TPM1 system.
Table 81. Prescale divisor selection
PS2:PS1:PS0
TPM1 Clock Source Divided-By
0:0:0
1
0:0:1
2
0:1:0
4
0:1:1
8
1:0:0
16
1:0:1
32
1:1:0
64
1:1:1
128
11.4.2 Timer counter registers (TPM1CNTH:TPM1CNTL)
The two read-only TPM1 counter registers contain the high and low bytes of the value in
the TPM1 counter. Reading either byte (TPM1CNTH or TPM1CNTL) latches the contents
of both bytes into a buffer where they remain latched until the other byte is read. This
allows coherent 16-bit reads in either order. The coherency mechanism is automatically
restarted by an MCU reset, a write of any value to TPM1CNTH or TPM1CNTL, or any
write to the timer status/control register (TPM1SC).
Reset clears the TPM1 counter registers.
Table 82. Timer counter register high (TPM1CNTH) (address $0011)
Bit
7
6
5
4
3
2
1
0
R
Bit 15
14
13
12
11
10
9
Bit 8
W
Any write to TPMCNTH clears the 16-bit counter.
Reset
0
0
0
0
0
0
0
0
Table 83. Timer counter register low (TPM1CNTL) (address $0012)
Bit
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Any write to TPMCNTL clears the 16-bit counter.
Reset
0
0
0
0
0
0
0
0
When BACKGROUND mode is active, the timer counter and the coherency mechanism
are frozen such that the buffer latches remain in the state they were in when the
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