NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
55 / 183
8.2 Pin behavior in STOP modes
Pin behavior following execution of a STOP instruction depends on the STOP mode that
is entered. An explanation of pin behavior for the various STOP modes follows:
•
In STOP1 mode, all internal registers including general purpose I/O control and data
registers are powered off. Each of the pins assumes its default reset state (input buffer,
output buffer and internal pullup disabled). Upon exit from STOP1, all pins must be
reconfigured the same as if the MCU had been reset.
•
In STOP4 mode, all pin states are maintained because internal logic stays powered up.
Upon recovery, all pin functions are the same as before entering STOP4.
8.3 General purpose I/O registers
This section provides information about the registers associated with the general purpose
I/O ports and pin control functions. These general purpose I/O registers are located in
page zero of the memory map and the pin control registers are located in the high page
register section of memory.
8.4 Port A registers
Port A general purpose I/O function is controlled by the registers described in this
section.
Table 55. Port A data register (PTAD) (address $0000)
Bit
7
6
5
4
3
2
1
0
R
W
PTAD[4:0]
Reset
0
0
0
0
0
0
0
0
= Reserved
Table 56. Port A data register field descriptions
Field
Description
4:0
PTAD[4:0]
Port A Data Register Bit — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level
is driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
Note:
PTA4 can be used as output-only.
Table 57. Internal pullup enable for port A register (PTAPE) (address $0001)
Bit
7
6
5
4
3
2
1
0
R
W
PTAPE[3:0]
Reset
0
0
0
0
0
0
0
0
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