NXP Semiconductors FXTH87E Reference Manual Download Page 51

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NXP Semiconductors

FXTH87E

FXTH87E, Family of Tire Pressure Monitor Sensors

FXTH87ERM

All information provided in this document is subject to legal disclaimers.

Reference manual

Rev. 5.0 — 4 February 2019

51 / 183

Bit

FRC_TIMER[7:0]

Reset

= Reserved

7.11.7.1 Software handler requirements

Application developers should adhere to the following steps when entering and exiting

software handler for the FRC:
1. Disable all interrupt sources

2. Write PMCT[0] = 1

3. Control PMCT and/or read FRC_TIMER as needed

4. Write PMCT[0] = 0

5. Enable all interrupt sources.

7.11.7.2 Initialization recommendations

Due to being clocked by the LFO which operates contentiously while power is applied,

application developers that desire the FRC to start from 0x0000 may initialize the FRC by

the following process:
1. Disable all interrupt sources

2. Write PMCT[0] = 1

3. Write PMCT[5] = 0 and PMCT[7] = 1

4. Write PMCT[5] = 1

5. Write PMCT[0] = 0

6. Re-enable appropriate interrupt sources.
These steps can be ignored if the application does not require the FRC to start from

0x0000.

7.12 System STOP exit status register (SIMSES)

The SIMSES register at $180D can be used to determine the source of an MCU

wakeup from the STOP modes. The flags are as shown in

Table 52

. All of the flags are

automatically cleared when the MCU goes into a STOP mode. Writes to any of these bits

are ignored.

Table 52. SIM STOP exit status (SIMSES) (address $180D)

Bit

KBF

IRQF

TRF

PWUF

LFF

RFF

Reset

= Reserved

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Summary of Contents for FXTH87E

Page 1: ...les representatives for performance attributes such as electrical mechanical and time based characteristics 2 Product profile 2 1 General description The FXTH87E is a small 7 x 7 mm fully integrated t...

Page 2: ...e GPIO pins Four pins can be connected to optional internal pullups pulldowns and STOP4 wakeup interrupt Two of seven pins can be connected to a channel on the ADC10 Two of seven pins can be connected...

Page 3: ...ge 11 cc 11 X axis 90 g range Z axis 300 g range cc 12 cc 12 X axis 90 g range Z axis 400 g range d Single digit or alphabetic character d Number or letter marketing suffix A Z a z or 0 9 2 5 Part mar...

Page 4: ...2 CHAN LVD RTI TIMER MCU CORE S08 AVDD TEMP TEMP SENSOR AVDD AVSS PRESS SENSOR LFA PTA1 ADC10 10 BIT 6 CHAN BKGD PTA4 LFB 64 BYTE PARAMETER REGISTER XI XO RF MCU TRANSDUCERS TEMP RESTART OSC BIT RATE...

Page 5: ...The various clock sources and their distribution are shown in Figure 2 All clock sources except the low frequency oscillator LFO can be turned off by software control in order to conserve power aaa 02...

Page 6: ...ure port up The orientation of the internal Z axis accelerometer is shown in Figure 4 PTA3 LFA LFB BKGD PTA4 X0 X1 PTB1 PTA2 PTA1 RESET VDD VDDA VSSA VREG RF PTB0 N C N C N C N C N C ID feature on top...

Page 7: ...D PTA4 15 BACKGROUND DEBUG mode enable LFB 16 LF receiver differential input channel B LFA 17 LF receiver differential input channel A PTA3 18 General purpose I O N C 19 20 21 22 23 No Connect Do not...

Page 8: ...lication to ensure the pressure applied to all surfaces of the sensor remains equal The sensor is constructed from nonhermetic materials and should not be used as a seal between the tire pressure and...

Page 9: ...AVSS and RVSS pins using a star connection such that each metal trace does not share any load currents with other external devices as shown in Figure 6 FXTH87E VDD Bypass capacitors closely coupled to...

Page 10: ...map to keyboard Interrupt function bits 1 0 4 4 9 PTA 3 2 pins The PTA 3 2 pins are general purpose I O pin These two pins can be configured as normal bidirectional I O pin with programmable pullup or...

Page 11: ...1 0 pins The PTB 1 0 pins are general purpose I O pins The PTB 1 0 pin functions become high impedance when the LF receiver has been enabled These two pins can be configured as nominal bidirectional I...

Page 12: ...while the user program is running Non intrusive commands can be issued through the BKGD PTA4 pin while the MCU is in RUN mode non intrusive commands can also be executed when the MCU is in the ACTIVE...

Page 13: ...n VLVDH or VLV DL rising VDD must rise above the LVI re arm voltage Upon wakeup from STOP1 mode the MCU will start up as from a power on reset POR by taking the reset vector Note If there are any pend...

Page 14: ...es Specific to the tire pressure monitoring application the parameter registers and the LFO with wakeup timer are powered up at all times whenever voltage is applied to the supply pins The LFR detecto...

Page 15: ...power is applied to the supply pins The contents of the parameter registers behave like RAM and are unaffected by any reset 5 5 4 4 LFO The LFO remains active regardless of any mode of operation 5 5...

Page 16: ...ture restart will remain powered up if the TRE bit is set If the temperature restart level is reached the MCU will restart from the reset vector 5 5 5 RFM module in STOP modes The RFM s external cryst...

Page 17: ...Parameter registers DFE0 DFDF User flash 8160 bytes User vectors Firmware flash 7008 bytes E000 DFFF E0A0 E09F Firmware jump table FBFF FC00 Protected coefficients 512 bytes Firmware flash 432 bytes...

Page 18: ...irst 80 locations in the memory map these are accessible with efficient direct addressing mode instructions The parameter registers begin at address 0050 these are also accessible with efficient direc...

Page 19: ...TAD 4 0 0001 PTAPE PTAPE 3 0 0002 Reserved 0003 PTADD PTADD 3 0 0004 PTBD PTBD 1 0 0005 PTBPE PTBPE 1 0 0006 Reserved 0007 PTBDD PTBDD 1 0 0008 Reserved 0009 Reserved 000A Reserved 000B Reserved 000C...

Page 20: ...FCDTM 3 0 0023 LFCTL4 LFDRIE LFERIE LFCDIE LFIDIE DECEN VALEN TIMOUT 1 0 0024 LFS LFDRF LFERF LFCDF LFIDF LFOVF LFEOMF LPSM LFIAK 0025 LFDATA RXDATA 7 0 0026 LFIDL ID 7 0 0027 LFIDH ID 15 8 Table 9 LF...

Page 21: ...RFD7 RFD 63 56 0044 RFD8 RFD 71 64 0045 RFD9 RFD 79 72 0046 RFD10 RFD 87 80 0047 RFD11 RFD 95 88 0048 RFD12 RFD 103 96 0049 RFD13 RFD 111 104 004A RFD14 RFD 119 112 004B RFD15 RFD 127 120 004C Reserv...

Page 22: ...004F Reserved Note Shaded bits are recommended to only be controlled by firmware or factory test 6 4 High address registers High page registers are used much less often so they are located above 1800...

Page 23: ...008F These registers are powered up at all times and may be used to store temporary or history data during the times that the MCU is in any of the STOP modes The parameter register at 008F is used by...

Page 24: ...cy read accesses 6 7 2 Program and erase times Before any program or erase command can be accepted the FLASH clock divider register FCDIV must be written to set the internal clock for the FLASH module...

Page 25: ...y time after the write to the memory array and before writing the 1 that clears FCBEF and launches the complete command Aborting a command in this way sets the FACCERR access error flag which must be...

Page 26: ...rrent command completes then the charge pump will be disabled and high voltage removed from the array Start Write to FLASH to buffer address and data Write command to FCMD No Yes FPVIOL or FACCERR Wri...

Page 27: ...ERR in FSTAT before any command can be processed Writing to a FLASH address before the internal FLASH clock frequency has been set by writing to the FCDIV register Writing to a FLASH address while FCB...

Page 28: ...tionally by the application software FPROT can be written through background debug commands which allows a way to erase and reprogram a protected FLASH memory The block protection mechanism is illustr...

Page 29: ...return all 0s Security is engaged or disengaged based on the state of nonvolatile register bits SEC 1 0 in the FOPT register During reset the contents of the nonvolatile location NVOPT are copied from...

Page 30: ...ce by taking these steps 1 Disable any block protections by writing FPROT FPROT can be written only with BACKGROUND DEBUG commands not from application software 2 Mass erase FLASH if necessary 3 Blank...

Page 31: ...clock divided by 8 if PRDIV8 1 by the value in the 6 bit DIV5 DIV0 field plus one The resulting frequency of the internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH...

Page 32: ...tches the nonvolatile backdoor key NVBACKKEY through NVBACKKEY 7 in that order security is temporarily disengaged until the next MCU reset 6 FNORED Vector Redirection Disable When this bit is 1 then v...

Page 33: ...t 7 6 5 4 3 2 1 0 R FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS W 1 1 1 1 1 1 1 1 Reset This register is loaded from nonvolatile location NVPROT during reset 1 Background commands can be used to change t...

Page 34: ...empt was made to erase or program a protected location 4 FACCERR Access Error Flag FACCERR is set automatically when the proper command sequence is not obeyed exactly the erroneous command is ignored...

Page 35: ...for easy reference A few reset and interrupt sources including the computer operating properly COP watchdog and real time interrupt RTI are not part of on chip peripheral systems but are part of the s...

Page 36: ...eset by writing any value to the address of SRS This write does not affect the data in the read only SRS Instead the act of writing to this address is decoded and sends a reset signal to the COP timer...

Page 37: ...SR because the ISR could continue to be executed periodically even if the main application program fails When the MCU is in ACTIVE BACKGROUND DEBUG mode or either Stop1 or Stop4 modes the COP timer is...

Page 38: ...WI instruction and consists of Saving the CPU registers on the stack Setting the I bit in the CCR to mask further interrupts Fetching the interrupt vector for the highest priority interrupt that is cu...

Page 39: ...addresses Towards LOWER addresses 7 0 1 2 3 4 5 5 4 3 2 1 High byte H of index register is not automatically stacked Figure 12 Interrupt stack frame 7 5 2 Vector summary Table 31 provides a summary of...

Page 40: ...mpletely sent 9 DFEC DFED Vrf RFM RFEF RFIEN Interrupt from the RFM when transmission error detected 8 DFEE DFEF Vsmi SMI SMIF SMIIE Interrupt from the Sensor Measurement Interface when the channel se...

Page 41: ...voltage drops below the VPOR level the POR circuit will cause a reset condition As the supply voltage rises the LVD circuit will hold the chip in reset until the supply has risen above the level dete...

Page 42: ...s The keyboard interrupts can be used to wake the MCU These are assigned to specific general I O pins as given in Table 33 Note Regarding wake up from Stop1 the reset vector is accessed taking precede...

Page 43: ...ck source is the LFO 1 Real time interrupt request clock source is the HFO MCU must be in the RUN mode 4 RTIE RTIF Interrupt Enable The RTIE bit enables RTI interrupts if written with a one Reset clea...

Page 44: ...registers in the high page register space are related to reset and interrupt systems 7 11 1 System Reset Status Register SRS The SRS register at 1800 includes seven read only status flags to indicate...

Page 45: ...er 0 Reset not caused by an illegal opcode 1 Reset caused by an illegal opcode 3 ILAD Illegal Address This bit indicates reset was caused by an attempt to access either data or an instruction at an un...

Page 46: ...either a very high or very low temperature This bit is cleared by an MCU reset 0 Temperature restart disabled 1 Temperature restart enabled 2 TRH Temperature Restart Level This control bit selects wh...

Page 47: ...leared by a reset and can be written at any time 00 Bus Frequency 4 MHz HFO 8 MHz 01 Bus Frequency 2 MHz HFO 4 MHz 10 Bus Frequency 1 MHz HFO 2 MHz 11 Bus Frequency 0 5 MHz HFO 1 MHz 7 11 4 System Pow...

Page 48: ...he BGBE bit is used to enable an internal buffer for the band gap voltage reference for use by the ADC module on one of its internal channels 0 Band gap buffer disabled 1 Band gap buffer enabled 7 11...

Page 49: ...LVWF Low Voltage Warning Flag The LVWF bit indicates the low voltage warning status 0 Low voltage warning not present 1 Low voltage warning is present or was present 6 LVWACK Low Voltage Warning Ackn...

Page 50: ...es 1808 and 1809 revert to the PMCRSC and PMCSC1 registers and the FRC remains functioning as last controlled while FPAGE had been 1 1 PMCT bits 7 and 5 functions as described above and addresses 1808...

Page 51: ...MCU goes into a STOP mode Writes to any of these bits are ignored Table 52 SIM STOP exit status SIMSES address 180D Bit 7 6 5 4 3 2 1 0 R KBF IRQF TRF PWUF LFF RFF W Reset 0 0 0 0 0 0 0 0 Reserved Dow...

Page 52: ...Port B registers for additional details regarding mutually exclusive operations The peripheral modules have priority over the general purpose I O so that when a peripheral is enabled the general purpo...

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Page 54: ...o avoid a floating input that could cause excessive supply current IDD When the device comes out of the reset state the NXP supplied firmware will not configure any of the general purpose I O pins Rec...

Page 55: ...rites are latched into all bits of this register For port A pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTAD to all 0s but these 0s are not...

Page 56: ...block is disabled port B pins operate as described here Table 61 Port B data register PTBD address 0004 Bit 7 6 5 4 3 2 1 0 R W PTBD 1 0 Reset 0 0 0 0 0 0 0 0 Reserved Downloaded from Arrow com Downlo...

Page 57: ...descriptions Field Description 1 0 PTBDD 1 0 Data Direction for Port B Bit n These read write bits control the direction of port B pins and what is read for PTBDD reads 0 Input output driver disabled...

Page 58: ...BACKGROUND mode When the microcontroller is in ACTIVE BACKGROUND mode the KBI will continue to operate normally 9 3 Block diagram The block diagram for the keyboard interrupt module is shown in Figure...

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Page 60: ...select control bits Table 72 KBI edge select register address 000E Bit 7 6 5 4 3 2 1 0 R W KBEDG3 KBEDG2 KBEDG1 KBEDG0 Reset 0 0 0 0 0 0 0 0 Downloaded from Arrow com Downloaded from Arrow com Downloa...

Page 61: ...ted to the CPU Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC 9 6 2 Edge and level sensitivity A valid edge or level on an enabled KBI pin will set KBF in KBISC If KBIE in KBISC is s...

Page 62: ...tions treat X as a second general purpose 8 bit register Seven addressing modes Inherent Operands in internal registers Relative 8 bit signed offset to branch destination Immediate Operand in next obj...

Page 63: ...registers H and X which often work together as a 16 bit address pointer where H holds the upper byte of an address and X holds the lower byte of the address All indexed addressing mode instructions u...

Page 64: ...rrupt and return operations load the program counter with an address other than that of the next sequential location This is called a change of flow During reset the program counter is loaded with the...

Page 65: ...result setting bit 7 of the result Simply loading or storing an 8 bit or 16 bit value causes N to be set if the most significant bit of the loaded or stored value was 1 0 Non negative result 1 Negati...

Page 66: ...inue at the branch destination address 10 4 3 Immediate addressing mode IMM In immediate addressing mode the operand needed to complete the instruction is included in the object code immediately follo...

Page 67: ...e instruction as the address of the operand needed to complete the instruction 10 4 6 6 SP Relative 8 Bit Offset SP1 This variation of indexed addressing uses the 16 bit value in the stack pointer SP...

Page 68: ...e routine After the CCR contents are pushed onto the stack the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine Although it is possible to clear the I bit wit...

Page 69: ...e Recovery from STOP mode depends on the particular HCS08 and whether the oscillator was stopped in STOP mode Refer to the Section 5 Modes of operation for more details 10 5 5 BGND instruction The BGN...

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Page 71: ...evaluates to a 16 bit value Because the HCS08 has a 16 bit address bus this can be either a signed or an unsigned value rel Any label or expression that refers to an address that is within 128 to 127...

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Page 82: ...2 DIR 44 1 LSRA 1 INH 54 1 LSRX 1 INH 64 5 LSR 2 IX1 74 4 LSR 1 IX 84 1 TAP 1 INH 94 2 TXS 1 INH A4 2 AND 2 IMM B4 3 AND 2 DIR C4 4 AND 3 EXT D4 4 AND 3 IX2 E4 3 AND 2 IX1 F4 3 AND 1 IX Downloaded fr...

Page 83: ...2 DIR 2F 3 BIH 2 rel 3F 5 CLR 2 DIR 4F 1 CLRA 1 INH 5F 1 CLRX 1 INH 6F 5 CLR 2 IX1 7F 4 CLR 1 IX 8F 2 WAIT 1 INH 9F 1 TXA 1 INH AF 2 AIX 2 IMM BF 3 STX 2 DIR CF 4 STX 3 EXT DF 4 STX 3 IX2 EF 3 STX 2 I...

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Page 85: ...LK 1 0 unused 1 1 Internal DX pin 11 2 1 Block diagram Figure 18 shows the structure of a TPM1 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com D...

Page 86: ...onal information about shared pin functions Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com...

Page 87: ...s CPWMS 0 All TPM channels operate as input capture output compare or edge aligned PWM mode as selected by the MSnB MSnA control bits in each channel s status and control register 1 All TPM channels o...

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Page 90: ...election CPWMS MS0B MS0A ELS0B ELS0A Mode Configuration X XX 00 Pin not used for TPM1 channel use as an external clock for the TPM1 or revert to general purpose I O 01 Capture on rising edge only 10 C...

Page 91: ...LS1A Reset 0 0 0 0 0 0 0 0 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from A...

Page 92: ...as a software timer that does not require the use of a pin Table 93 Mode edge and level selection CPWMS MS1B MS1A ELS1B ELS1A Mode Configuration X XX 00 Pin not used for TPM1 channel use as an externa...

Page 93: ...or A 16 bit modulo register also is associated with Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Ar...

Page 94: ...wed The enable signal selects between software polling TOIE 0 where no hardware interrupt is generated or interrupt driven operation TOIE 1 where a static hardware interrupt is automatically generated...

Page 95: ...f a 16 bit register have been written This coherency sequence can be manually reset by writing to the channel status control register TPM1CnSC An output compare event sets a flag bit CHnF that can opt...

Page 96: ...tive bit 15 set the duty cycle will be 0 If TPM1CnVH TPM1CnVL is a positive value bit 15 clear and is greater than the nonzero modulus setting the duty cycle will be 100 because the duty cycle compare...

Page 97: ...cy mechanism for TPM1C0VH TPM1C0VL 11 6 TPM1 interrupts The TPM1 generates an optional interrupt for the main counter overflow and an interrupt for each channel The meaning of channel interrupts depen...

Page 98: ...ing timer interrupt flags When a channel is configured as an output compare channel the interrupt flag is set each time the main timer counter matches the 16 bit value in the channel value register Th...

Page 99: ...rt them into an 8 bit 9 bit or 10 bit transfer function These measurement accuracy specifications cannot be guaranteed if the user creates custom software routines to convert these measurements For ad...

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Page 101: ...tion regarding the recommended use of the accelerometer self test features Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow...

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Page 107: ...dic reset of the MCU Both the wakeup time counter and the periodic reset timer are incrementing counters that generate their interrupt or reset when the desired count is Downloaded from Arrow com Down...

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Page 114: ...e sampling time during the off time 14 4 Input amplifier The LFR module receives LF modulated signals through a dedicated differential pair of inputs which is connected to an external coil The enable...

Page 115: ...until it is cleared before it continues the alternating cycle of on time and off time starting with an off time In data mode when a carrier is detected the averaging filter is powered on and the LFR c...

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Page 117: ...logic zero or a logic one The LFRO clock source is 32 times the target data rate The LFRO is used for decoding data and also sequencing auto zero operations Downloaded from Arrow com Downloaded from...

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Page 121: ...mation When power is applied to the MCU the LFR must be initialized and configured before it can begin to receive LF messages Several systems in the LFR require factory trimming Downloaded from Arrow...

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Page 125: ...ery 1 ms Therefore LFR detection times of 1024 2048 4096 and 8192 sec the auto zero sequence will be done at each 1 ms interval This auto zero sequence lasts for 64 sec If the carrier is detected agai...

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Page 152: ...ow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded...

Page 153: ...aded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow co...

Page 154: ...Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloa...

Page 155: ...from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Do...

Page 156: ...ed from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com...

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Page 159: ...rrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloade...

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Page 162: ...ownloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arr...

Page 163: ...nloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow...

Page 164: ...wnloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arro...

Page 165: ...d from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com D...

Page 166: ...ded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com...

Page 167: ...row com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded...

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Page 169: ...rom Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Down...

Page 170: ...nloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow...

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Page 172: ...Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Download...

Page 173: ...ed from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com...

Page 174: ...row com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded...

Page 175: ...m Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downlo...

Page 176: ...ed version of a document is for reference only The English version shall prevail in case of any discrepancy between the translated and English versions 20 3 Trademarks Notice All referenced brands pro...

Page 177: ...wnloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arro...

Page 178: ...0 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from...

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Page 181: ...oaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow c...

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Page 183: ...nloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow...

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