NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
182 / 183
13.3
PWU control/status register 0 — PWUCS0
(address $0039) ............................................ 108
13.4
PWU control/status register 1 — PWUCS1 ....110
13.5
PWU wakeup status register — PWUS ......... 110
13.6
Functional modes .......................................... 111
13.6.1
RUN mode .....................................................111
13.6.2
STOP4 mode .................................................111
13.6.3
STOP1 mode .................................................111
13.6.4
Active BDM/foreground commands ............... 112
14
LF Receiver ......................................................112
14.1
Features .........................................................113
14.2
Modes of operation ........................................114
14.3
Power management .......................................114
14.4
Input amplifier ................................................ 114
14.5
LFR data mode states ...................................115
14.6
Carrier detect .................................................115
14.7
Auto-zero sequence .......................................117
14.8
Data recovery ................................................ 117
14.9
Data clock recovery and synchronization .......117
14.10
Manchester decode ....................................... 118
14.11
Duty-cycle for data mode .............................. 118
14.12
Input signal envelope .....................................119
14.13
Telegram verification ..................................... 120
14.14
Error detection and handling ......................... 121
14.15
Continuous ON mode ....................................121
14.16
Initialization information ................................. 121
14.17
LFR register definition ................................... 122
14.17.1 LF control register 1 (LFCTL1) ...................... 122
14.17.2 LF control register 2 (LFCTL2) ...................... 123
14.17.3 LF control register 3 (LFCTL3) ...................... 124
14.17.4 LFR control register 4 (LFCTL4) ....................126
14.17.5 LFR status register (LFS, LPAGE = 0) .......... 127
14.17.6 LFR data register (LFDATA, LPAGE = 0) ...... 128
14.17.7 LFR ID registers (LFIDH:LFIDL, LPAGE = 0) ..129
14.17.7.1 LF Control E — LFCTRLE .............................129
14.17.8 LFR control register D (LFCTRLD, LPAGE =
1) ....................................................................130
14.17.9 LFR control register C (LFCTRLC, LPAGE =
1) ....................................................................131
14.17.10 LFR control register B (LFCTRLB, LPAGE =
1) ....................................................................132
14.17.11 LFR control register A (LFCTRLA, LPAGE =
1) ....................................................................132
15
RF module ....................................................... 133
15.1
RF data modes ..............................................134
15.1.1
RF data buffer mode ..................................... 134
15.1.2
MCU direct mode .......................................... 135
15.2
RF output buffer data frame .......................... 135
15.2.1
Data buffer length ..........................................136
15.2.2
End of Message (EOM) .................................136
15.3
Transmission randomization ..........................136
15.3.1
Initial time interval ..........................................137
15.3.2
Interframe time intervals ................................ 138
15.3.3
Base time interval ..........................................138
15.3.4
Pseudo-random time interval .........................138
15.3.5
Frame number time ....................................... 139
15.4
RFM in STOP1 mode ....................................140
15.5
Data encoding ............................................... 140
15.5.1
Manchester encoding .................................... 140
15.5.2
Bi-Phase encoding .........................................140
15.5.3
NRZ encoding ................................................141
15.6
RF output stage .............................................143
15.6.1
Modulation method ........................................ 143
15.6.2
Carrier frequency ...........................................143
15.6.3
RF power output ............................................143
15.6.4
Transmission error .........................................144
15.6.5
Supply voltage check during RF
transmission ...................................................144
15.6.6
RF Reset (RFMRST) .....................................144
15.7
RF interrupt ....................................................144
15.8
Datagram transmission times ........................ 144
15.9
RFM registers ................................................ 145
15.9.1
RFM Control Register 0 — RFCR0 ............... 145
15.10
RFM control register 1 — RFCR1 ................. 145
15.11
RFM control register 2 — RFCR2 ................. 146
15.11.1 Power working domains ................................ 147
15.11.1.1 PTYP ..............................................................147
15.11.1.2 PMIN ..............................................................147
15.12
RFM control register 3 — RFCR3 ................. 148
15.13
RFM control register 4 — RFCR4 ................. 149
15.14
RFM control register 5 — RFCR5 ................. 149
15.15
RFM control register 6 — RFCR6 ................. 150
15.16
RFM control register 7 — RFCR7 ................. 150
15.17
PLL control registers A - PLLCR[1:0],
RPAGE = 0 ....................................................152
15.18
PLL control registers B - PLLCR[3:2],
RPAGE = 0 ....................................................153
15.19
EPR register — EPR (RPAGE = 1) ............... 154
15.20
RF DATA registers — RFD[31:0] ...................154
15.21
VCO calibration machine ...............................155
16
Firmware .......................................................... 156
16.1
Software jump table .......................................156
16.2
Function documentation ................................ 156
16.2.1
General rules ................................................. 157
16.2.1.1 FXTH87E single Z-axis firmware routines ......157
16.2.1.2 FXTH87E dual XZ-axis firmware routines ......158
16.2.2
Device identification .......................................160
16.2.3
Definition of signal ranges ............................. 161
16.3
Memory resource usage ................................163
16.3.1
Software stack ............................................... 163
17
Development support ..................................... 163
17.1
Introduction .................................................... 163
17.1.1
Features .........................................................163
17.2
Background debug controller (BDC) ..............163
17.2.1
BKGD/PTA4 pin description .......................... 164
17.2.2
Communication details .................................. 165
17.2.3
BDC commands .............................................167
17.2.3.1 Coding structure nomenclature ......................167
17.2.4
BDC hardware breakpoint ............................. 169
17.3
Register definition ..........................................169
17.3.1
BDC registers and control bits .......................169
17.3.2
BDC status and control register (BDCSCR) ... 170
17.3.3
BDC breakpoint match register (BDCBKPT) .. 171
17.3.4
System background debug force reset
register (SBDFR) ........................................... 171
18
Battery charge consumption modeling .........172
18.1
Standby current ............................................. 172
18.2
Measurement events ..................................... 172
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