NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
93 / 183
CPWMS
MS1B:MS1A
ELS1B:ELS1A
Mode
Configuration
10
High-true pulses (clear output on compare)
1x
x1
Edge-aligned
PWM
low-true pulses (set output on compare)
10
High-true pulses (clear output on compare-up)
1
XX
x1
Center-aligned
PWM
low-true pulses (set output on compare-up)
If the associated port pin is not stable for at least two bus clock cycles before changing
to input capture mode, it is possible to get an unexpected indication of an edge trigger.
Typically, a program would clear status flags after changing channel configuration bits
and before enabling channel interrupts or using the status flags to avoid any unexpected
behavior.
11.4.7 Timer channel value registers (TPM1C1VH:TPM1C1VL)
These read/write registers contain the captured TPM1 counter value of the input capture
function or the output compare value for the output compare or PWM functions. The
channel value registers are cleared by reset.
Table 94. Timer channel 1 value register high (TPM1C1VH) (address $0019)
Bit
7
6
5
4
3
2
1
0
R
W
Bit 15
14
13
12
11
10
9
Bit 8
Reset
0
0
0
0
0
0
0
0
Table 95. Timer channel 1 value register low (TPM1C1VL) (address $001A)
Bit
7
6
5
4
3
2
1
0
R
W
Bit 7
6
5
4
3
2
1
Bit 0
Reset
0
0
0
0
0
0
0
0
In input capture mode, reading either byte (TPM1C1VH or TPM1C1VL) latches the
contents of both bytes into a buffer where they remain latched until the other byte is read.
This latching mechanism also resets (becomes unlatched) when the TPM1C1SC register
is written.
In output compare or PWM modes, writing to either byte (TPM1C1VH or TPM1C1VL)
latches the value into a buffer. When both bytes have been written, they are transferred
as a coherent 16-bit value into the timer channel value registers. This latching
mechanism may be manually reset by writing to the TPM1C1SC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to
various compiler implementations.
11.5 Functional description
All TPM1 functions are associated with a main 16-bit counter that allows flexible selection
of the clock source and prescale divisor. A 16-bit modulo register also is associated with
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
