NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
108 / 183
reached and are then reset to zero. Reading the status of either of these counters will
return a zero content if done immediately after the interrupt or reset is generated.
If both the reset and the interrupt occur on the same clock cycle the reset will have
precedence and the interrupt will not be generated.
In order to prevent wakeup or reset from an extreme temperature event both the wakeup
interrupt or periodic reset are disabled if the thermal restart is activated and the TRO bit
indicates that the device is still outside of the T
RESET
range. The wakeup and periodic
reset counters will still run. The state of these counters can be read using the PSEL bit in
the PWUS register.
The wakeup interrupt (WUKI) cannot be masked by clearing the I-bit.
13.2 Wakeup divider register — PWUDIV
The PWUDIV register contains six bits to select the division of the incoming 1 ms clock
period as described in
Table 97
.
Table 97. PWU divider register (PWUDIV) (address $0038)
Bit
7
6
5
4
3
2
1
0
R
0
0
W
WDIV[5:0]
Reset
—
—
—
—
—
—
—
—
POR
0
0
0
1
1
1
1
1
= Reserved
Table 98. PWUDIV register field descriptions
Field
Description
7:6
Unused
Unused
5:0
WDIV[5:0]
Wakeup Divider Value — The WDIV[5:0] bits select an incoming prescaler for the incoming 1 ms clock
period from 504 to 1512.
This results in a clocking of the 6-bit wakeup divider at rates from a nominal 0.504 to 1.512 sec per wakeup
clock, WCLK. The user can use this prescaler to fine tune the wakeup time based on the variation in the
LFO frequency. The conversion from the decimal value of the WDIV bits to the nominal WCLK period is
given as:
A power on reset presets these bits to a value of $1F (decimal 31) which yields a nominal 1 second output
period for WCLK. Other resets have no effect on these bits.
13.3 PWU control/status register 0 — PWUCS0 (address $0039)
The PWUCS0 register contains six bits to select the division of the incoming WCLK clock
period and provide interrupt flag and acknowledge bits as described in
Table 99
. The
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