NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
24 / 183
When security is enabled, the RAM is considered a secure memory resource and is
not accessible through BDM or through code executing from non-secure memory. See
Section 6.8 "Security"
for a detailed description of the security feature.
None of the RAM locations are used directly by the firmware provided by NXP. The
firmware routines utilize RAM only through stack operations; and the user needs to be
aware of stack depth required by each routine as described in the CodeWarrior project
files supplied by NXP.
6.7 FLASH
The FLASH memory is intended primarily for program storage. The operating program
can be loaded into the FLASH memory after final assembly of the application product
using the single-wire BACKGROUND DEBUG interface. Because no special voltages
are needed for FLASH erase and programming operations, in-application programming
is also possible through other software-controlled communication paths. For a more
detailed discussion of in-circuit and in-application programming, refer to the HCS08
Family Reference Manual, Volume I, NXP document number HCS08RMV1/D.
6.7.1 Features
Features of the FLASH memory include:
•
User Program FLASH Size — 8192 bytes (16 pages of 512 bytes each)
•
Single power supply program and erase
•
Command interface for fast program and erase operation
•
Up to 100,000 program/erase cycles at typical voltage and temperature
•
Flexible FLASH protection
•
Security feature for FLASH and RAM
•
Auto power-down for low-frequency read accesses
6.7.2 Program and erase times
Before any program or erase command can be accepted, the FLASH clock divider
register (FCDIV) must be written to set the internal clock for the FLASH module to a
frequency (f
FCLK
) between 150 kHz and 200 kHz. This register can be written only once,
so normally this write is performed during reset initialization. FCDIV cannot be written if
the access error flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR
is not set before writing to the FCDIV register. One period of the resulting clock (1/f
FCLK
)
is used by the command processor to time program and erase pulses. An integer number
of these timing pulses are used by the command processor to complete a program or
erase command.
Table 13
shows program and erase times. The bus clock frequency and FCDIV
determine the frequency of FCLK (f
FCLK
). The time for one cycle of FCLK is t
FCLK
= 1/
f
FCLK
. The times are shown as a number of cycles of FCLK and as an absolute time for
the case where t
FCLK
= 5 μs. Program and erase times shown include overhead for the
command state machine and enabling and disabling of program and erase voltages.
Table 13. Program and erase times
Parameter
Cycles of FCLK
Time if FCLK = 200 kHz
Byte program
9
45 μs
Byte program (burst)
4
20 μs
[1]
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