NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
52 / 183
Table 53. SIMSES register field descriptions
Field
Description
7-6
Reserved
Reserved Bits — These bits are reserved for NXP firmware control. Application software shall assure that
this bit is never overwritten.
5
KBF
Keyboard Flag — This bit indicates that any keyboard pin caused the last exit from STOP mode.
0 Keyboard pin did not cause the last exit from STOP mode
1 Keyboard pin caused the last exit from STOP mode
4
IRQF
IRQ Flag — This bit indicates that IRQ pin caused the last exit from STOP mode.
0 IRQ pin did not cause the last exit from STOP mode
1 IRQ pin caused the last exit from STOP mode
3
TRF
Temperature Restart Flag — This bit indicates that the temperature restart module caused the last exit from
STOP mode.
0 TR module did not cause the last exit from STOP mode
1 TR module caused the last exit from STOP mode
2
PWUF
PWU Flag — This bit indicates that the PWU module caused the last exit from STOP mode.
0 PWU module did not cause the last exit from STOP mode
1 PWU module caused the last exit from STOP mode
1
LFF
LFR Flag — This bit indicates that the LFR module caused the last exit from STOP mode.
0 LFR module did not cause the last exit from STOP mode
1 LFR module caused the last exit from STOP mode
0
RFF
RFM Flag — This bit indicates that the RFM module caused the last exit from STOP mode.
0 RFM module did not cause the last exit from STOP mode
1 RFM module caused the last exit from STOP mode
8 General Purpose I/O
This section explains software controls related to general purpose input/output (I/O) and
pin control. The FXTH87E has seven general-purpose I/O pins which are comprised of a
general use 5-bit port A and a 2-bit port B.
PTA[4:0] pins are shared with on-chip peripheral functions. PTB[1:0] pins are GPIO only
and are mutually exclusive with the LF receiver, such that PTB[1:0] pins become high
impedance when the LF is enabled (see
Section 8.5 "Port B registers"
for additional
details regarding mutually exclusive operations). The peripheral modules have priority
over the general purpose I/O so that when a peripheral is enabled, the general purpose
I/O functions associated with the shared pins are disabled. After reset, the shared
peripheral functions are disabled so that the pins are controlled by the general purpose
I/O. All of the general purpose I/O are configured as inputs (PTxDDn = 0) with pullup
devices disabled (PTxPEn = 0).
To avoid extra current drain from floating input pins, the user’s application software
must configure these pins so that they do not float (see
Section 8.1 "Unused pin
configuration"
).
Reading and writing of general purpose I/O is performed through the port data registers.
The direction, either input or output, is controlled through the port data direction registers.
The general purpose I/O port function for an individual pin is illustrated in the block
diagram in
Figure 13
.
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